Transcript Network on Chip Architecture Project Summary and Key

Network on Chip
Architecture
Project Summary
and Key
Achievements
Kari Tiensyrjä
VTT Electronics
Oulu, Finland
Kari Tiensyrjä
NOCARC project
EXSITE Workshop
Helsinki, Finland, 20.11.2002
1
Outline
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Research Objectives
Research Organisation
Key Achievements
Publications, Dissemination and Co-operation
Future Plans
Conclusions
Kari Tiensyrjä
EXSITE Workshop
Helsinki, Finland, 20.11.2002
2
Research Objectives
•
In 2008, a Network-on-Chip (NoC) can have billion transistors, and
accommodate tens of computer like resources (1 NoC > 200 SoCs, 1 NOC
capacity  100-10000 GIPS, …)
Research hypothesis is that current architectures and design approaches
do not scale enough
10 computers
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Objectives
• Novel architecture template called network
on chip, i.e. NOC for future integrated
telecommunication systems
• Design methodology that supports definition
of application specific architecture,
configuration of architecture and cooptimisation of both architecture and
applications
11 computers
Kari Tiensyrjä
EXSITE Workshop
Helsinki, Finland, 20.11.2002
3
Research Organisation
• Workpackages
VINNOVA
TEKES
H. Håkansson
EXSITEProgram
Ericsson
B. Hadjiski
Nokia
Spirea
NOCARC
Steering Group
A. Hemani
KTH
A. Jantsch
J. Tanskanen
K. Kronlöf
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WP1 NoC Concept
WP2 NoC Architecture
WP3 Decision Support
WP4 Quality Estimation
WP5 Design Tools
• Figures
VTT
S. Kumar NOCARC
K. Tiensyrjä
M. Millberg Project M. Forsell
J-P. Soininen
J. Öberg
Group J. Kreku
R. Thid
T. Salminen
E. Nilsson
– 2001 -2003
– ~ € 1000000
– ~ 10 person years
• Further Information
– http://www.ele.kth.se/NOC/
Kari Tiensyrjä
EXSITE Workshop
Helsinki, Finland, 20.11.2002
4
Key Achievements
• Milestone “NoC Concept paper” has been achieved, and
published in ISVLSI2002
– NoC architecture principles: topology, network, resources,
communication, regions
– Design methodology: backbone, platform, system
• NoC architecture studies have been published in IEEE Micro,
JSA, WSEAS2002, SSGRR2002w, NorChip2002 and submitted to
DATE2003
– Network communication for NoC: simulator, protocol stack, switch
– Parallel computer for NoC: multi-threaded processor, memory structures,
switch, functional simulator
– Physical feasibility issues: wire-ability, timing, power distribution
• NoC decision support and quality estimation studies have been
published in DATE2002, CODES2002, DSD2002, NorChip2002 and
accepted to VLSI2003
Kari Tiensyrjä
EXSITE Workshop
Helsinki, Finland, 20.11.2002
5
Publications, Dissemination and Co-operation
• 21 papers
– 3 journal papers published, 1 accepted, 1 (with COMPLAIN) submitted
– 12 conference papers published, 1 accepted, 3 submitted
– 1 magazine paper
• Theses, tutorials, training, reports
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3 MSc theses
ESSCIRC2001 tutorial (with COMPLAIN)
KTH SoC master programme lectures (with COMPLAIN)
2 technical reports
• “NoC Book” (with COMPLAIN and external experts) to appear 2003
– Contribution to 6 chapters (out of 15)
• 3 steering group, 5 technical, 2 working meetings, researcher
visits
Kari Tiensyrjä
EXSITE Workshop
Helsinki, Finland, 20.11.2002
6
Future Plans
• Research work continues in WP2-5 according to research plan
ID Task Name
2 NOC Concept
3 NOC Concept paper
Qtr 4
2001
Qtr 1 Qtr 2 Qtr 3
Qtr 4
Qtr 1
2002
Qtr 2 Qtr 3
Qtr 4
2003
Qtr 1 Qtr 2 Qtr 3
Qtr 4
Qtr 1
20
Qtr 2
30.9
4 NOC Architecture
5 NOC definition paper
30.6
6 NOC architecture paper
30.6
7 Decis ion Support
8 Quality Es timation
9 Decis ion&Estimation paper
31.12
10 NOC Design Tools
11 NOC Methodology paper
31.12
12 Adminis tration
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15
Kari Tiensyrjä
EXSITE Workshop
Helsinki, Finland, 20.11.2002
7
Conclusions
• 1 billion transistor NoCs are expected to be used in products
by 2008
– Network communication, tens or even hundreds of computer-like
resources in heterogenous case, homogeneous parallel computers
– Complexity of a NoC equals to that of a board in current basestation
• Development of such a NoC system will be a huge effort
– Reuse has to be enhanced through regular structures and layered
design methodology
– Backbone, platform, system based design methodology approach
provides variability, performance and cost-efficiency
• Each layer of the design methodology should follow a pattern:
Analysis - Decision - Estimation - Validation
– Related methods are the cornerstones of NOC development
– Tool support for decision making, quality estimation and validation
Kari Tiensyrjä
EXSITE Workshop
Helsinki, Finland, 20.11.2002
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