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ASIC design seminar
Jonny Johansson
EISLAB, CSEE, LTU
20100323
Todays agenda
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09.00 Introduction to ASIC design
09.45 Coffee
10.00 On the Fraunhofer Institute
11.00 An applied example
11.40 Walk through lab
12.00 Lunch
Short words on CSEE and EISLAB
Jonny Johansson
Computer Science and Electrical Engineering
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8 research topics
~35 faculty
~55 PhD students
~105 employees
250 full time students
Turn over EUR 10 million
– Undergraduate education EUR 1,5 million
– Research EUR 8,5 million
CSEE – education
• Undergraduate education in Computer science and
Engineering physics and electronics
• International cooperation with exchange and
masters students
• Two years int’l masters programmes
– M.Sc. in Mobile Systems
CSEE – Research subjects
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Automatic Control
Computer Communication
Embedded Systems
Computer Science
Industrial Electronics
Media Technology
Medical Technology
Signal Processing
About EISLAB
• EISLAB (Embedded Internet Systems Laboratory)
is a division within the Dept. of Computer Science
and Electrical Engineering.
• Our work includes research and education in the
fields of electronics, embedded systems, sensors,
and robotics.
EISLAB by the numbers
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Research leaders: Prof. Jerker Delsing, Prof. Per Lindgren
Manager: Dr. Jan van Deventer
Faculty: 14 people.
+25 PhD students
Other staff: 5 people.
Yearly research turnaround: EUR 4 Million.
Research areas at EISLAB
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Embedded EMC
– Simulation and experimental methods for electromagnetic
problems
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Sensor Systems
– Sensing using ultrasonics, optics, and GNSS
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Electronics Design
– Analog and mixed signal ASIC and discrete electronics design for
sensor systems
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Electronics production
– Solderability and testability for small and medium volume
production
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EIS architecture
– Methodologies, tools, and realizations of Embedded Internet
Systems
ASIC design at EISLAB
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Staff
– Who do?
• Johan B, Jonny J, Hans Raben
– Who did?
• Kirill, Martin G, Lei Zou,
– Who will?
• Håkan F, Kalevi, New PhD student within ESIS
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Courses
– ASIC deisgn course for students in 3rd or 4th year
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Research
– ESIS; Elektronik system - ett regionalt innovationssystem
– CMTF; Centrum för medicinsk teknik och fysik
Introduction to ASIC design
What is an ASIC?
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On-chip combination of analog and digital building
blocks
– Analog: amplifiers, comparators, charge pumps
– Digital: counters, memory, state machines etc
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Can be an autonomous system!
Integrated Circuit – IC
– Standard components, e.g. op-amps, uP etc
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Application Specific IC - ASIC
– Custom made for specific application
– This is what we do!
Why ASIC?
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Size
– Thousands of transistors in one mm2
– Easy integration in e.g. sensor systems
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Power consumption
– Low internal loads
– Full control over power partitioning
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Performance
– High speeds
– Stringent timing
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Features not realizable with discrete components
– Charge Coupled Devices – CCD
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Price?
– Only economical for very large volumes
Europractice – an important resource
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Supports microelectronics development & research within EU
– Small business, universities and research organizations
– Good connections; Fraunhofer IIS is coordinator
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Design software
– All major brands, we use Cadence
– Research, prototypes, and small volume!
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Chip design via a number of foundries
– We use austriamicrosystems, AMS
– Very good design support
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http://www.europractice-ic.com/
Process and cost examples
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Multi project wafer – MPW
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Several designs on same wafer – lower cost for masks
Fhg IIS & IMEC coordinates
We receive 20-40 dies, bare or encapsulated
EISLAB up to now in about 10 MPW runs
AMS 0.35 µm CMOS technology
– 4 metal layers
– 3.3 Volt
– € 580 / mm2 (min € 5,800)
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UMC 0.18 µm CMOS technology
– 6 metal layers
– 1.8 / 3.3 Volt
– € 920 / mm2 (min € 23,000)
The microelectronics laboratory
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From bare die to
tested system!
Initial investment
by Kempe
Running cost
funded by user
projects
Mounting
- Chip i package
- Chip on PCB
- SMT
Fault tracing
- On-chip probing
Elektrical connection
- Wire bondning
- Conductive glue
- Soldering
System level test
- Signal generators
- Oscilloscopes
- Logic analyzer
Analog and digital design flows
Analog
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Few to tens of transistors
Constraints
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Digital
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– Noise, speed, power
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Designer starts from scratch
Manual schematic entry
Manual layout
Manual wiring
Highly dependent on parasitics
Matching critical
Complex tools
Thousands of transistors
Constraints
– Timing, size
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Designer writes “code”
Automatic schematic generation
Automatic layout
Automatic wiring
Almost non-dependent on parasitics
Matching uncritical
Complex tools
Specification
Analog design flow
• Specification
Initial design
Simulation
Layout
Post-layout sim.
Manufatcure
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Analog inverter
Noise
Speed
Loads
Slew rate
Power consumption
Process choice
Specification
Analog design flow
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Initial design
Initial design
– Schematic entry
– Some parts simulated at higher level (AHDL)
VDD
Simulation
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T1
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Layout
Vout
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T2
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Post-layout sim.
Manufatcure
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Specification
Analog design flow
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Initial design
Simulation
Layout
Simulation
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Initial simulations to verify design approach
Tune design to work over “corners”
Temperature, process variation, supply changes
Values can vary several tens of % !
vOUT
Post-layout sim.
Manufatcure
vIN
Specification
Analog design flow
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Initial design
Simulation
Layout
Layout
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Artwork with rectangles
About 20 layers to work with
Transistors predefined
Matching issues critical
Cross-verify with schematic
GND
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VDD
Post-layout sim.
Manufatcure
Out
NMOS
PMOS
Specification
Analog design flow
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Initial design
Simulation
– Extract R & C from layout
– Re-simulate
– Iterate
Simulation
vOUT
Layout
Post-layout sim.
Manufatcure
vIN
Specification
Analog design flow
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Initial design
Simulation
Layout
Post-layout sim.
Manufatcure
Manufacture
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Generate layout data file
Send to Europractice for check
Wait three months…
Power up and cross your fingers
Verification tricky on-chip
Design entry
Digital design flow
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Set constraints
Synthesis
Placement
Routing
Manufatcure
Design Entry
– Develop VHDL or Verilog files
– Simulation at functional level
Design entry
Digital design flow
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– AMS 0.35 µm CMOS technology
– UMC 0.18 µm CMOS technology
Set constraints
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Synthesis
Placement
Routing
Manufatcure
Specify technology
Set constraints
– E.g. clock frequency or area
– 100 MHz
– Max 2.0 mm2
Design entry
Digital design flow
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Set constraints
Synthesis
Placement
Routing
Manufatcure
Synthesis
– Generates schematic based on standard cells
– Schematic is described by new code
Design entry
Digital design flow
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Set constraints
Synthesis
Placement
Routing
Manufatcure
Placement
– Designer gives “floorplan”
– Pad ring, where to place cells etc
– Tool places standard cells after “code”
Design entry
Digital design flow
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Set constraints
Synthesis
Placement
Routing
Manufatcure
Routing
– Tool creates all interconnect
Design entry
Digital design flow
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Set constraints
Synthesis
Placement
Routing
Manufatcure
Manufacture
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Generate layout data file
Send to Europractice for check
Wait three months…
Power up and cross your fingers
Design examples
A 16-bit 60µW Multi-Bit ΣΔ Modulator
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Targeting portable ECG applications
Low bandwidth, extremely low power
High dynamic range
Low signal (6 mV) high offsets (300
mV)
On chip clock generation logic
Achieves 16 bit DR
Three channel complete system
inplemented by Fhg IIS
HV transmit/receive chip for US application
Pump
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Discharge
Amp.
Aux. Amp.
FSM
AMS HV 0.8 µm CMOS
High voltage generation for
excitation (up to 40 V from 3 V
supply)
Amplifier for received echo
State machine for chip control
Operating time of several years
from single Lithium battery
possible
Size 3.5 x 3.5 mm
Ctrl.
Low time jitter comparator for level crossing ADC
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Level crossing ADC measures time for
signal level crossing
Requires high stability comparator
10 bit SNR can be achieved with 16
levels
Time jitter 100 ps at 6 ns propagation
time
CCD test chip
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Used as analog memory
FIFO, 190 elements
Idea: Capture hig speed signals
for subsequent AD conversion
Allow the rest of the system to
remain sleep mode until data
identified
New vesrions ready for
evaluation
SPAD - Single photon avalanche diode
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Receiver for laser distance
measurement
Detects single photons at
about 10% probability
Reverse bias “above”
avalanche breakdown
Single photon triggers
breakdown
Tested in lab
High voltage high current DAC
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Driver for US applications
Up to 40 V p-p, 400 mA max
150 MHz sampling frequency
High precision timing and
current
• On chip calibration
• On chip HV switches for offchip receiver isolation
That’s it, questions?