Transcript Lecture 11 - Survey of Reconfigurable Logic Technologies

ECE 448
Lecture 11
Survey of Reconfigurable
Logic Technologies
ECE 448 – FPGA and ASIC Design with VHDL
George Mason University
Resources
Xcell Journal
available for FREE on line
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FPGA and Structured ASIC Journal
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Technology Timeline
1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
Transistors
ICs (General)
SRAMs & DRAMs
Microprocessors
SPLDs
CPLDs
ASICs
FPGAs
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Programmable Logic Devices
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First Programmable Logic Devices
PLDs
SPLDs
PROMs
PLAs
CPLDs
PALs
GALs
etc.
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Programmable logic device as a black box
Inputs
(logic variables)
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Logic gates
and
programmable
switches
Outputs
(logic functions)
6
General structure of a PLA
(Programmable Logic Array)
x1 x2
xn
Input
buffers
& inverters
x1 x1
xn xn
P1
AND plane
OR plane
Pk
f1
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fm
7
Gate-level diagram of a PLA
x1
x2
x3
Programmable
connections
P1
OR plane
P2
P3
P4
AND plane
f1
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f2
8
Customary schematic for a PLA
x1
x2
x3
OR plane
P1
P2
P3
P4
AND plane
f1
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f2
9
Programmable Array Logic
x1
x2
x3
P1
f1
P2
P3
f2
P4
AND plane
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Macrocell at the output of PAL
Select
Enable
f1
Flip-flop
D
Q
Clock
To AND plane
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A generic structure of CPLD
(Complex Programmable Logic Device)
Programmable
Interconnect
matrix
Input/output pins
SPLD-like
blocks
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PAL-like
block
PAL-like
block
I/O block
I/O block
Structure of a CPLD
PAL-like
block
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PAL-like
block
I/O block
I/O block
Interconnection wires
13
A section of a CPLD
PAL-like block
D Q
D Q
D Q
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Connections between the programmable
interconnect matrix and simple PAL-like blocks
100 wires
Programmable
multiplexer
30 wires
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Field Programmable
Gate Arrays
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General structure of an FPGA
Programmable
interconnect
Programmable
logic blocks
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Xilinx CLB
Configurable logic block (CLB)
CLB
CLB
CLB
CLB
Slice
Slice
Logic cell
Logic cell
Logic cell
Logic cell
Slice
Slice
Logic cell
Logic cell
Logic cell
Logic cell
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Simplified view of a Xilinx Logic Cell
16-bit SR
16x1 RAM
a
b
c
d
4-input
LUT
e
y
mux
flip-flop
q
clock
clock enable
set/reset
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RAM Blocks and Multipliers in Xilinx
FPGAs
RAM blocks
Multipliers
Logic blocks
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Embedded Microprocessor Cores
uP
uP
uP
uP
uP
(a) One embedded core
(b) Four embedded cores
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Virtex-II Pro Architecture
2
3
Features:
1.
2.
3.
4.
5.
6.
Processor Block
RocketIO Multi-Gigabit
Transceivers
CLB and Configurable Logic
SelectIO-Ultra
Digital Clock Managers
Multipliers and Block
SelectRAM
1
6
4
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22
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Processor Block
• Contains four components:
BRAM
• Processor Local Bus (PLB)
• On-chip Peripheral Bus (OPB)
• Device Control Register
(DCR) Bus
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Control
PPC 405
Core
Interface Logic
BRAM
FPGA CLB Array
• IBM CoreConnect Bus
Architecture Features:
BRAM
OCM Controller
OCM Controller
• Embedded IBM PowerPC
405-D5 RISC CPU core
• On-Chip Memory (OCM)
controllers and interface
• Clock/control interface logic
• CPU-FPGA Interfaces
BRAM
24
PowerPC Cores
PowerPC
System
PowerPC
System
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Embedded Development Kit (EDK)
Software Flow
Hardware Flow
Processor IP,
Microprocessor
Peripheral
Description Files
VHDL /
Verilog
C / C++
Code
Libraries
PlatGen
Synthesizer
Compiler
LibGen
Microprocessor
Hardware
Specification
File
EDIF IP
Netlists
Object Files
Microprocessor
Software
Specification File
ISE /
Xflow
Linker
System
Constraint
File
Bitstream
Data2MEM
Executable
Download to FPGA
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A simple clock tree
Clock
tree
Flip-flops
Special clock
pin and pad
Clock signal from
outside world
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Clock Manager
Clock signal from
outside world
Clock
Manager
etc.
Daughter clocks
used to drive
internal clock trees
or output pins
Special clock
pin and pad
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Jitter
1
2
3
4
Ideal clock signal
Real clock signal with jitter
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Superimposed cycles
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Removing Jitter
Clock signal from
outside world
with jitter
Clock
Manager
etc.
“Clean” daughter
clocks used to drive
internal clock trees
or output pins
Special clock
pin and pad
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Frequency Synthesis
1.0 x original clock frequency
2.0 x original clock frequency
.5 x original clock frequency
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Phase shifting
0o Phase shifted
90o Phase shifted
180o Phase shifted
270o Phase shifted
Figure 4-20
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Removing Clock Skew
Daughter clock (monitored
downstream of the clock manager)
fed back to special input
Clock signal from
outside world
De-skewed daughter
clocks used to drive
internal clock trees
or output pins
Special clock
pin and pad
1
2
3
4
Main (mother) clock
1
2
3
4
Untreated daughter clock
1
2
3
De-skewed daughter clock
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General-Purpose IO Blocks
1
0
2
7
General-purpose I/O
banks 0 through 7
3
6
4
5
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Using High-Speed Tranceivers to
Communicate Between Devices
Transceiver block
Differential pairs
FPGA
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Programming Reconfigurable
Logic Devices
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A Fusible Link Technologies:
Unprogrammed Device
Fuses
Logic 1
Fat
a
Pull-up resistors
Faf
NOT
Fbt
b
&
y = 0 (N/A)
AND
Fbf
NOT
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A Fusible Link Technologies:
Programmed Device
Logic 1
Fat
a
Pull-up resistors
NOT
&
b
y = a & !b
AND
Fbf
NOT
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An Antifuse Technology:
Unprogrammed Device
Unprogrammed
antifuses
a
Logic 1
Pull-up resistors
NOT
b
&
y = 1 (N/A)
AND
NOT
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An Antifuse Technology:
Programmed Device
Programmed
antifuses
a
Logic 1
Pull-up resistors
NOT
b
&
y = !a & b
AND
NOT
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Growing an Antifuse
Amorphous silicon column
Polysilicon via
Metal
Oxide
Metal
Substrate
(a) Before programming
(b) After programming
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EPROM Technology
Source
terminal
Control gate
terminal
Drain
terminal
Source
terminal
Control gate
terminal
Drain
terminal
control gate
Silicon
dioxide
control gate
source
drain
(a) Standard MOS transistor
Silicon
substrate
floating gate
source
drain
(b) EPROM transistor
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An EPROM Transistor-Based Memory Cell
Logic 1
Pull-up resistor
Row
(word) line
EPROM
Transistor
Logic 0
Column
(data) line
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EEPROM Technology
E2PROM
transistor
Normal
MOS transistor
E2PROM Cell
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Static RAM-based Technology
SRAM
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Summary of Programming Technologies
Technology
Symbol
Predominantly
associated with ...
Fusible-link
SPLDs
Antifuse
FPGAs
EPROM
SPLDs and CPLDs
E2PROM/
FLASH
SPLDs and CPLDs
(some FPGAs)
SRAM
SRAM
FPGAs (some CPLDs)
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Feature
SRAM
Antifuse
E2PROM /
FLASH
Technology node
State-of-the-art
One or more
generations behind
One or more
generations behind
Reprogrammable
Yes
(in system)
No
Yes (in-system
or offline)
Reprogramming
speed (inc.
erasing)
Fast
----
3x slower
than SRAM
Volatile (must
be programmed
on power-up)
Yes
No
No
(but can be if required)
Requires external
configuration file
Yes
No
No
Good for
prototyping
Yes
(very good)
No
Yes
(reasonable)
Instant-on
No
Yes
Yes
IP Security
(especially when using
bitstream encryption)
Very Good
Very Good
Size of
configuration cell
Large
(six transistors)
Very small
Medium-small
(two transistors)
Power
consumption
Medium
Low
Medium
Rad Hard
No
Yes
Not really
Acceptable
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SRAM FPGA Configuration
•
Loading the bitstream into internal memory by delivering it through one of the
configuration interfaces
•
Configuration phases:
1.
2.
3.
4.
Clearing the configuration memory
Initialization
Bitstream loading
Device startup
Configuration Device
Bitstream
A series of
command
and data
101110
101011
100101
001010
011101
SRAM FPGA
• JTAG
• SelectMAP
• Slave/Master Serial
• ICAP
Correspond to
configuration modes
Configuration
Interface
Configuration
Logic
Configuration
Memory
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Configuration of SRAM based FPGAs
Configuration data in
Configuration data out
= I/O pin/pad
= SRAM cell
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FPGA Configuration Modes
Mode Pins
Mode
0
0
0
Serial load with FPGA as master
0
0
1
Serial load with FPGA as slave
0
1
0
Parallel load with FPGA as master
0
1
1
Parallel load with FPGA as slave
1
x
x
Use only the JTAG port
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Serial Load with FPGA as a Master
FPGA
Memory
Device
Control
Configuration data in
Cdata In
Cdata Out
Configuration
data out
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Daisy-Chaining FPGAs
Memory
Device
Control
FPGA
FPGA
Cdata In
Cdata In
Cdata Out
Cdata Out
etc.
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Parallel Load with FPGA as a Master
(off-the-shelf memory)
Memory
Device
Control
FPGA
Address
Configuration data [7:0]
Cdata In[7:0]
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Parallel Load with FPGA as a Master
(special-purpose memory)
Memory
Device
Control
Configuration data [7:0]
FPGA
Cdata In[7:0]
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Microprocessor
Peripheral,
Port, etc.
Memory
Device
Parallel Load with FPGA as a Slave
Control
Address
FPGA
Data
Cdata In[7:0]
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Using the JTEG Port
JTEG = Joint Test Action Group, IEEE 1149.1
JTAG data out
JTAG data in
From previous
JTAG filp-flop
To internal
logic
Input pad
Input pin from
outside world
JTAG flip-flops
From internal
logic
To next
JTAG filp-flop
Output pin to
outside world
Output pad
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Internal Processor Boundary Scan Chain
JTAG data out
JTAG data in
FPGA
Primary scan chain
Internal (core) scan chain
Core
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Reconfiguration Interfaces in Xilinx FPGAs
Internal Port
ICAP
(Virtex-II)
JTAG
SelectMap
(8 bits Parallel)
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Configuration times
of selected FPGA
devices
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