Transcript Ch 5 - Personal.kent.edu

Chapter 5: Computer Systems
Organization
Invitation to Computer Science,
Objectives
In this chapter, you will learn about:

The components of a computer system

Putting all the pieces together – the Von
Neumann architecture

The future: non-Von Neumann architectures
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Introduction
• Remember that Computer science is the study of algorithms
including
•
Their formal and mathematical properties (Chapter 1-3)
•
their hardware realization (Chapter 4-5)
•
Their linguistic realizations.
•
Their applications.

Computer organization examines the computer as a collection of
interacting “functional units”

Functional units may be built out of the circuits already studied

Higher level of abstraction assists in understanding by reducing
complexity
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Figure 5.1
The Concept of Abstraction
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The Components of a Computer System

Von Neumann architecture has four functional units:

Memory


Input/Output


The unit that stores and retrieves instructions and data.
Handles communication with the outside world.
Sequential execution of instructions

Arithmetic/Logic unit


Performs mathematical and logical operations.
Control unit

Repeats the following 3 tasks repeatedly
1.
2.
3.

Fetches an instruction from memory
Decodes the instruction
Executes the instruction
Stored program concept
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Figure 5.2
Components of the Von Neumann Architecture
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Memory and Cache

Information stored and fetched from memory
subsystem

Random Access Memory (RAM) maps
addresses to memory locations

Cache memory keeps values currently in use in
faster memory to speed access times
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Memory and Cache (continued)

RAM (Random Access Memory)

Memory made of addressable “cells”

Current standard cell size is 1 byte = 8 bits

All memory cells accessed in equal time

Memory address

The address is an unsigned binary number N long 
Address space is then 2N cells
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Memory and Cache (continued)

Memory Size


Memory size is in power of 2

210 =1K
1 kilobyte

220 =1M
1 megabyte

230 =1G
1 gigabyte

240 =1T
1 terabyte
If the MAR is N digits long, the largest address is….?

The maximum memory size for a MAR with

N = 16 is..?
_______________

N = 20 is..?
_______________

N = 31 is..?
________________
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Figure 5.3
Structure of Random Access Memory
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Memory and Cache (continued)

Parts of the memory subsystem

Fetch/store controller

Fetch: retrieve a value from memory

Store: store a value into memory

Memory address register (MAR)

Memory data register (MDR)

Memory cells, with decoder(s) to select individual
cells
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Decoder Circuit

A decoder is a control circuit which has


N input and 2N output
0
A 3 to 23 example of decoder
1
a
0
0
0
0
1
1
1
1
b
0
0
1
1
0
0
1
1
c o0 o1 o2 o3 o4
0 1 0 0 0 0
1 0 1 0 0 0
0 0 0 1 0 0
1 0 0 0 1 0
0 0 0 0 0 1
1 0 0 0 0 0
0 0 0 0 0 0
1 0 0 0 0 0
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o5
0
0
0
0
0
1
0
0
o6
0
0
0
0
0
0
1
0
o7
0
0
0
0
0
0
0
1
2
3
4
5
6
7
a
b
c
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Memory and Cache (continued)

Fetch operation
1.
Load the address in to the MAR

2.
The address of the desired memory cell is moved into the MAR
Decode the address in the MAR


Fetch/store controller signals a “fetch,” accessing the memory cell.
The memory unit must translate the N-bit address stored in the MAR
into the set of signals needed to access that one specific memory cell

3.
A decoder circuit is used for such a purpose
Copy the content of the memory location into the MDR

The value at the MAR’s location flows into the MDR
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Memory and Cache (continued)
Store operation

1.
Load the address into the MAR

2.
Load the value into the MDR

3.
The address of the cell where the value should go is placed in
the MAR
The new value is placed in the MDR
Decode the address in the MAR and store the content of
the MDR into that memory location

Fetch/store controller signals a “store,” copying the MDR’s
value into the desired cell
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Example: The Units Of A Computer
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Fetch: LOAD X
f
D
X
D
LOAD X
D
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Store: STORE X
s
D
X
D
STORE X
D
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Memory and Cache (continued)

Memory register

Very fast memory location

Given a name, not an address

Serves some special purpose

Modern computers have dozens or hundreds of
registers
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Figure 5.7
Overall RAM Organization
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Cache Memory

Memory access is much slower than processing
time

Faster memory is too expensive to use for all
memory cells

Locality principle


Once a value is used, it is likely to be used again
Small size, fast memory just for values currently
in use speeds computing time
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Input/Output and Mass Storage


Communication with outside world and external
data storage

Human interfaces: monitor, keyboard, mouse

Archival storage: not dependent on constant
power
External devices vary tremendously from each
other
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Input/Output and Mass Storage
(continued)

Volatile storage



Information disappears when the power is turned off
Example: RAM
Nonvolatile storage


Information does not disappear when the power is
turned off
Example: mass storage devices such as disks and
tapes
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Input/Output and Mass Storage
(continued)

Mass storage devices


Direct access storage device

Hard drive, CD-ROM, DVD, etc.

Uses its own addressing scheme to access data
Sequential access storage device

Tape drive, etc.

Stores data sequentially

Used for backup storage these days
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Input/Output and Mass Storage
(continued)

Direct access storage devices

Data stored on a spinning disk

Disk divided into concentric rings (sectors)

Read/write head moves from one ring to another
while disk spins

Access time depends on:

Time to move head to correct sector

Time for sector to spin to data location
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Figure 5.8
Overall Organization of a Typical Disk
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Input/Output and Mass Storage
(continued)

I/O controller

Intermediary between central processor and I/O
devices

Processor sends request and data, then goes on
with its work

I/O controller interrupts processor when request is
complete
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Figure 5.9
Organization of an I/O Controller
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The Arithmetic/Logic Unit

Actual computations are performed

Primitive operation circuits

Arithmetic (ADD, etc.)

Comparison (CE, etc.)

Logic (AND, etc.)

Data inputs and results stored in registers

Multiplexor selects desired output
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Multiplexor

A multiplexor is a control circuit that selects one of the input lines to
allow its value to be output.


A multiplexor It has 2N input lines, N selector lines and one output.



To do so, it uses the selector lines to indicate which input line to
select.
The N selector lines are set to 0s or 1s. When the values of the N
selector lines are interpreted as a binary number, they represent the
number of the input line that must be selected.
With N selector lines you can represent numbers between 0 and 2N-1.
The single output is the value on the line represented by the
number formed by the selector lines.
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Multiplexor Circuit
2N input
lines
0
1
2
multiplexor
circuit
2N-1
.....
output
For our example,
the output is the
value on the line
numbered 1
N selector lines
Interpret the selector lines as a binary number.
Suppose that the selector line write the number 00….01
which is equal to 1.
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Multiplexor Circuit (continued)
multiplexor
with N=1
0
1
A multiplexor can be built with AND-OR-NOT gates
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RECALL: THE ARITHMETIC/LOGIC UNIT USES
A MULTIPLEXOR
R
Register R
Other registers
AL1
ALU
AL2
condition code register
circuits
multiplexor
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selector lines
GT EQ LT
output
(In the lab you will
see where this will 32go)
The Arithmetic/Logic Unit
(continued)

ALU process

Values for operations copied into ALU’s input
register locations

All circuits compute results for those inputs

Multiplexor selects the one desired result from all
values

Result value copied to desired result register
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Figure 5.12
Using a Multiplexor Circuit to Select the Proper ALU Result
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The Control Unit

Manages stored program execution

Task
1.
Fetch from memory the next instruction to be
executed
2.
Decode it: determine what is to be done
3.
Execute it: issue appropriate command to ALU,
memory, and I/O controllers
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Machine Language Instructions

Can be decoded and executed by control unit

Parts of instructions

Operation code (op code)


Unique unsigned-integer code assigned to each
machine language operation
Address field(s)

Memory addresses of the values on which
operation will work
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00001001
ADD
0000000001100011
X
0000000001100100
Y
Figure 5.14
Typical Machine Language Instruction Format
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Operations Available











Arithmetic Operations
load
store
clear
add
increment
subtract
decrement
I/0 Operations
in
out

Logic/Control
Operations

compare
jump
jumpgt
jumpeq
jumplt
jumpneq
halt






There is a different Operation Code (OpCode) for each Operation
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Machine Language Instructions
(continued)

Operations of machine language

Data transfer


Move values to and from memory and registers
Arithmetic/logic

Perform ALU operations that produce numeric
values
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Machine Language Instructions
(continued)

Operations of machine language (continued)

Compares


Set bits of compare register to hold result
Branches

Jump to a new memory address to continue
processing
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Control Unit Registers And Circuits

Parts of control unit

Links to other subsystems

Instruction decoder circuit

Two special registers:

Program Counter (PC)


Stores the memory address of the next instruction to
be executed
Instruction Register (IR)

Stores the code for the current instruction
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Figure 5.16
Organization of the Control Unit Registers and Circuits
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Putting All the Pieces Together—the
Von Neumann Architecture

Subsystems connected by a bus

Bus: wires that permit data transfer among them

At this level, ignore the details of circuits that
perform these tasks: Abstraction!

Computer repeats fetch-decode-execute cycle
indefinitely
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Figure 5.18
The Organization
of a Von Neumann
Computer
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The Control Unit
2) The fetch places
the instruction in
the IR.
5) As all instructions use the
address, except for halt, the
address is sent to either the
MAR or PC- which depends
on the instruction.
IR
PC
1 0 0 1 address
1) After a fetch,
the PC is
+1
incremented
by 1.
4) The decoder
sends out signals
for execution
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instruction
decoder
3) The opcode
is sent to the
decoder
line 9
enable add
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The Future: Non-Von Neumann
Architectures

Physical limitations on speed of Von Neumann
computers

Non-Von Neumann architectures explored to
bypass these limitations

Parallel computing architectures can provide
improvements: multiple operations occur at the
same time
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What are the fastest computer in the world?
Visit the site
http://www.top500.org/list/2005/06/
to find out!
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The Future: Non-Von Neumann
Architectures (continued)

SIMD architecture

Single instruction/Multiple data

Multiple processors running in parallel

All processors execute same operation at one
time

Each processor operates on its own data

Suitable for “vector” operations
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Figure 5.21
A SIMD Parallel Processing System
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The Future: Non-Von Neumann
Architectures (continued)

MIMD architecture

Multiple instruction/Multiple data

Multiple processors running in parallel

Each processor performs its own operations on its
own data

Processors communicate with each other
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Figure 5.22
Model of MIMD Parallel Processing
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Summary of Level 2

Focus on how to design and build computer
systems

Chapter 4

Binary codes

Transistors

Gates

Circuits
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Summary of Level 2 (continued)

Chapter 5

Von Neumann architecture

Shortcomings of the sequential model of
computing

Parallel computers
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Summary




Computer organization examines different
subsystems of a computer: memory,
input/output, arithmetic/logic unit, and control
unit
Machine language gives codes for each
primitive instruction the computer can perform,
and its arguments
Von Neumann machine: sequential execution of
stored program
Parallel computers improve speed by doing
multiple tasks at one time
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Examples of instructions: LOAD X
f
D
X
D
LOAD X
D
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STORE X
s
D
X
D
STORE X
D
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ADD X
f
D
X
E+D
E
E
E+D
D
ADD X
ALU1 & ALU2
D
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E+D
57
INCREMENT X
X
INC X
D+1
D
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COMPARE X
(assume D > E)
f
D
X
E
D
E
COM X
ALU1 & ALU2
D
1 0 0
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JUMP X
X
JUMP X
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JUMPLT X
X
JUMPLT X
0 0 1
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JUMPLT X
JUMPLT X
1 0 0
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Similarly for
condition
code of 0 1 0
62
IN X
s
D
X
D
IN X
D
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OUT X
f
D
X
D
OUT X
D
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