Transcript CMS_Pixel_Architecture_Horisberger - Indico

CMS Pixel Issues
ACES 07
Common ATLAS – CMS Electronics Workshop
CERN
20. March 2007
R. Horisberger
Paul Scherrer Institut
• SLHC Tracker / Detector upgrade in 2014/16 requires action already now !
• 7-9 years not terribly much for : -
Conception of SLHC tracker
Basic R&D
Prototyping
Demonstators
Production
Installation & Commissioning
• Should learn from current experience of LHC trackers !
Cabling/Cost/Cooling
• Present tracker is probably quite good , but too much material budget !
 Next tracker should do a factor 2 better !
• SLHC creates extra problems with: - data rates 10x
- event complexity 20x
- event selection  triggering with tracks
- radiation damage
• Present pixel detector conceived in 1996 / 97 with:
• focus on easy insertion/removal of pixel system
• keep material budget low
 achieved
1.93% X0/Layer (h=0)
• use analog optolinks of strip APV readout
 adaptation in geometry
• keep optolinks at maximum radius
 limit rad. damage
• Operate at L =1034 at radii 7cm & 11cm
 data rates, buffer size
• rad. hard DMILL technology 0.8mm  2 ½ metal layers
5.5V supply
BiCMOS (was useful)
 present pixel ROC architecture with :
1) Zero channel suppression (pixel hit discrimination)
2) Analog pulse height readout (~ 7-8 bit)
Readout : pixel address (5 clocks) + analog pulse height (1 clock)
Pixel readout
analog coded pixel address
Overlap of 4160 pixel readouts
1 pixel hit
1 clock cycle:
analog pulse height
chip
header
col#
pix#
5 clock cycles:
encode 13 bits of pixel
address information.
Present system: had to use analog optical link available !
Future SLHC system: digital bit stream through high speed link !
(add 1 ADC/ROC)
Column Drain Architecture
sketch of a double column
7.8mm
hit
pixel unit cells: 2x80
data
column drain
mechanism
double
column
fast double
column OR
set
double column
interface
data buffer
Depth: 32
Time-stamp buffer
Depth: 12
marker bits indicate
start of new event
32 data
buffers
12 time stamp
buffers
Transfer data rapidly to periphery and store for L1 latency ( ~3.4usec)
9.8mm
double
pixels
• DMILL pixel ROC worked !
Yield:
0 pixel defect
1-5 pixel defect
<1%
22%
• Translation DMILL ROC to 0.25um ROC with big financial & electrical benefits
DMILL
Wafer size
Wafer cost [CHF]
Yield
0.25m IBM
6”
12K
22% (<5px def.)
Ratio
8”
2.5K
70% (0 def.)
~2x (area)
~4x
~3x
Total :
Engineering run
~200K
~ 24 x Cost benefits
~160k
• Will the change from 0.25mm to 0.13mm give a similar benefit?
 No !
0.13um production wafers of same size (8”) are 60% more expensive
Engineering run ~ 3 times more expensive.
7900mm
0.25m Pixel ROC
• Chip modified to DMILL version
- should have uniform address levels
- external Operation is same
• Chip Internal Power Regulators
• Column Drain Architecture
• more timestamp & data buffers
8  12
24  32
now fit for r=4cm at L=1034
• less power  28mW/pixel
• smaller pixel area: 100m x 150m
Total # transistors : 1280 K
(DMILL 430K )
IBM_PSI46
Data losses of pixel ROC
• Original ROC design (TDR) was done for high lumi operation of 7cm layer!
• Use 0.25m ROC translation to optimize for new pixel size and 4cm radius !!
Data losses
DMILL ROC
0.25mm ROC
@ r=4cm & L=1034
DM_PSI43
IBM_PSI46
150m x 150m pixel
100m x 150m pixel
3.1%
0.17%
(8)
(12)
0.1%
0.15%
(# buffers)
(24)
(32)
Column Drain
load cycle
3%
0%
Timestamp
( # buffers)
Data Buffers
Column Drain
3rd hit capability
1.4%
0.25%
Pixel overwrite
0.3%
0.21%
SLHC Luminosity
Data loss due to limited
timestamp buffers &
data buffers
increase very quickly
e.g. 10 x LHC would need
60 timestamp buffers
Periphery size would
increase factor 5x
650m  ~ 3250m
SLHC Track Rate .vs. Radius
SLHC situation
1000
• Track rates at L = 10 35 cm-2 sec-1
y = 4560 x-1.5
Silicon Pixels Detector
LHC Rates
@10 34
SLHC Rates
@10 34
r = 4cm
r = 18cm
r = 7cm
r = 30cm
r = 11cm
r = 50cm
• Performance of present pixels at
SLHC?
Track Rate [MHz/cm^2]
•Technology already exists for
SLHC tracking at radii > 20cm :
100
10
1
0
10
20
30
40
50
60
70
Radius [cm]
80
90 100 110 120
Data loss mechanisms
Pixel busy:
0.04% / 0.08% / 0.21%
pixel insensitive until hit
transferred to data buffer
(column drain mechanism)
0.25m ROC
•
Double column busy:
0.004% / 0.02% / 0.25%
Column drain transfers hits
from pixel to data buffer.
Maximum 3 pending column
drains requests accepted
PSI46
1xLHC: 1034cm-2s-1
11 cm / 7 cm / 4 cm layer
total data loss @ 100kHz L1A:
0.8%
1.2%
3.8%
Pixel-column interface
Timestamp Buffer full:
0 / 0.001% / 0.17%
Data Buffer full:
0.07% / 0.08% / 0.17%
Readout and double column reset:
0.7% / 1% / 3.0%
for 100kHz L1 trigger rate
Double column readout
SLHC rate data losses dominated by finite buffer sizes !
 chip size !
periphery bigger
Influence of buffer size at r= 4cm layer
1.0000
Inefficiency
0.1000
1xLHC
2.5xLHC
5xLHC
10xLHC
0.0100
0.0010
0.0001
0
10
20
30
40
50
60
# timestamps
/ doublecolumn
# Timestamps/
Doublecolumn
• Present system: 12 time stamp buffers, 32 data buffers. Average pixel multiplicity:2.2
• Possible extension: doubling the buffer size (24/64). Enough for < 2.5x1034cm-2s-1
• For 10x1034 need 60 timestamp buffers and 190 data buffers (average pixel
multiplicity: 2.6).
Inefficiency for r= 4cm layer
100
• Timestamp- & Data- buffer limitations
removed
Data Loss
[%]
• Inefficiency < 7% up to 2.5x1034cm-2s-1
(as before)
• In 130nm technology column drain per
column possible (instead of double
columns) dashed lines
10
• 7% inefficiency at 4.5x1034cm-2s-1
1
DC busy
Readout + DC reset
Pixel busy
Column busy (new)
r/o + column reset (new)
0.1
1
2
3
4
5
6
7
Luminosity [ 10^34
[10]34]
8
9
10
Inefficiency for 10x1034 cm-2sec-1
• Cannot operate < 7cm
100
• For higher radii data loss
dominated by readout losses
Data Loss [%]
• Worse for higher L1 trigger rates
• Worse for higher trigger latencies
10
•  new parallel module readout
scheme
DC busy
1
readout + DC reset
Pixel busy
Column busy (new)
r/o +column reset
(new)
0.1
4
6
8
10
12
Radius [cm]
[cm]
Radius
14
16
18
SLHC rate tests of CMS Pixel Modules
• High rate tests in X-ray box allows hit rates up to 300 MHz/cm2
• Simulation of pixel read out
chip (ROC) compares quite
well with observed data loss
• We can identify the data
loss mechanisms
 finite data buffers
 readout times
• For SEU studies and
timewalk need to go to pion
beam line at PSI
 150 MHz/cm2
 20nsec bunch structure
LHC (1034cm-2s-1):
11cm
7cm
4cm
High rate data losses in x-ray test
• X-ray box (pix.mult.= 1)
 timestamp buffer
overflows dominant
• Pion beam (pix.mult.> 1)
 data buffer overflow
pixel overwrite
• Loss due to pixel overwrite
(~ pixel size) is not relevant
• Small pixels create large
data traffic !
LHC (1034cm-2s-1):
11cm
7cm
4cm
Doubing the buffer size in 0.25mm
mounting screw whole
0.4mm
new ROC size
• Doubling the buffer size in current ROC
 periphery increase of 800mm
 just possible
• No R&D needed. Design time ~ 1 month
Cold upgrade of replacement pixel modules produced in >2010
Evolutionary upgrade of CMS pixel modules
• CMS pixel modules need to be replaced. ( r=4cm every 2 years @ 1034)
• LHC  SLHC has probably no sharp step in luminosity
• Can improve rate capability of present pixel modules by:
- increase buffer size in ROC periphery (2x in 0.25mm CMOS, 5x in 0.13mm )
- extra data buffer in redesigned TBM with parallel ROC read out scheme
• Replaced modules would be fully compatible with present system.
 allows operation of present pixel system at L ~ 4x10
Present TBM Read Out Scheme
34
cm-2 sec-1
Future TBM Read Out Scheme
SLHC Pixel Tracking
(zero suppressed readout)
• What are our priorities: - tracker for 1035 but same X/X0 and resolution ?
- reduce material budget (X/X0) ?
- improve resolution (Dp/p , impact parameter) ?
- triggering ( jet, track selection, impact parameter) ?
• Financial envelope for new Super LHC tracker ~ 115 – 120 MCHF
• How many technologies are radially needed to deal with
- rates ( wide range)
- cost per unit area
- minimal power per layer  minimal material budget (X/X0)
• Present Pixel System has radii : r = 4cm 7cm 11cm
Layer cost go by area ~ r2 = 16
49
121
15cm was to costly
225
• Present pixel works well under high rates but cannot be financed for r >18cm !
• Increasing layer radius r  cost per surface must scale ~ 1/ r2 !
 use cheaper technology, just adequate for rate at this layer radius !
Costs of a CMS Pixel Barrel Module
Cables (40cm) & TBM etc.
100 SFr
HDI (High Density Interconnect)
300 SFr
Sensor (DS, n+ in n-Si)
800 SFr
Bump bonding
3200 SFr
16 Readout chips 0.25m
( DMILL:
250 SFr
7200 SFr )
Baseplate (SiN)
Module of Area = 10cm2
50 SFr
Costs ~ 4700 SFr
Optical links, FED , FEC, Power supplies add +15%  ~550 SFr/cm2
Costing Speculations
* = C4NP (IBM)
[CHF/cm2]
Pixel (now) Large pixels Macropixels MAPS
Pixel Area
Sensor/ROC
Tiling unit
0.015 mm2
1/1
10 cm2
Bumping
320
Sensors
80
ROC
25
HDI
30
Cables
8
Baseplate
5
Pitchadjust
0
Optical Link (1) 32
pxFED
25
Total
(1)
(2)
(3)
(4)
525
0.15 mm2
1/1
40 cm2
20*
10
50
30
8
5
0
6
4
~130
1.5 mm2
10 / 1
100 cm2
2*
10
2
3
0.8
0.5
15(2)
0.6
0.4
~35
~ 320 CHF/channel
~ 0.02 CHF/cm fine pitch trace
Yield speculations based on experience with DMILL SOI-wafers
Extra cost for anodic wafer bonding or SOI wafer growth
--0/1
4 cm2
0
0
50
30
8
5
0
6
4
~105
CMOS+Sensor
--1/1
4 cm2
0
10+10?(4)
200?(3)
30
8
5
0
32
25
~320?
C4NP Low Cost Bumping
Injection Molded Solder
(IBM & Süss)
IMS Principle
Mold
• IMS allows bump 75m size and pitch of 150m
• 200m thick wafers processed so far
• Wafer costs (300mm) ~ 150 $
Material budget & Supplies
Material budget for 3 Layers at h = 0
Current Pixel Barrel System:
• Bring power in
= 4%
(On-Chip regulators,Al-wire)
• Take power out = 29%
Cooling is material budget driver !
Low mass cooling and/or
Reduce power consumption !
X/X0 = 5.79% for 3 barrel pixel layers
 1.93% / layer
Current consumption:
Analog:
Strips  reduce noise
Pixels  speed (timewalk) ! !
Digital:
Information processing (data flow)
CMS ROC: ID = 32mA no tracks
ID = 40mA at 40MHz/cm2 track rate
• Reduce power by :
- Technology
CMOS 0.25m  0.13m
 Digital:
local: YES
 Analog: NO
global: NO
W.I. 
gm 
IDS
n  UT
on chip regulators
- Architecture choice
- Custom protocols
Pixel ROC Power :
ALICE
ATLAS
CMS*
CMS
466 mW/cm2
335 mW/cm2
194 mW/cm2
142 mW/cm2
no
no
yes
no
TBM05 ~ 1/6 power of TBM03
abandon LVDS for 5cm distance  custom
protocol LCDS (Low Current Differential Swing)
The next SLHC tracker must be very cautious and careful with power consumption !
Sensor capacitance & front end analog power dissipation
Spice simulation of present CMSPIX front end with fixed timewalk (<25nsec)
Time walk is
power driver
not noise !
Analog Current .vs. Pixel Capacitance
800
700
Analog Current [A]
Current for 65 Mega Pixel
900
600
500
400
300
200
100
0
0
50
100
150
200
250
300
350
Pixel Capacitance [fF]
measured pixel capacitance (n-pixel 100mm x 150mm, p-spray)
Estimate power consequences of sensor element size
Assume:
(for toy-tracker)
• 13 layer tracker with radii = 10 – 130 cm
• simple barrel – forward geometry , break at h=1.65
• Sensor capacity with fixed pitch variable length
Csens = const x length
 layer area = const x r2
Csens = 0.1 pF  3pF
pixel  strixel  strips
• Density of channels  N (r) ~ r2/Csens
• Analog power depends on sensor capacitance  Iana = Io + slope x Csens (prev. page)
• Digital power dependence on data traffic & particle fluence:
CMSPIX measured
 Idig = 32mA +
0.2 mA x fluence-rate [MHz/cm2]
Current per layer for 13 layer SLHC Pixel tracker
Current .vs. Cs & R
1
r = 10cm – 130cm
Csens
S Ilayers
[pF]
[Ampere]
0.1
0.1 -2.2
3.0
77.1 K
9.4 K (*)
5.4 K
Linear power
increase with
radius. Constant
cabling density
3
5
7
9
11
13
15
17
CCs
[pF]
sensor
19
[0.1pF]
21
23
25
27
29
S1
S5
S9
2000
1900
1800
1700
1600
1500
1400
1300
1200
1100
1000 Current [Ampere]
900
800
700
600
500
400
300
200
100
0
S13
Radius
[cm]
Layer radius
[x10cm]
Proposal for low power ohmic link
together with Optical Information Hubs
Optical links can have very large bandwidth  data hubs
Excellent for long distant (20-100m) information transfer.
e.g. 3.3Gbit/sec link with 1200mW/channel  360 pJ/bit
Optical cabling inside tracker region very painfull, due to variable length. (slack
management)
Data transfer inside sensitive tracker region has problem with:
1) Variable cable length typ. 10cm – 90cm
2) Individual tracking modules have modest information transfer
(~0.3Gbits/sec)
Need for 2 wire ohmic bidirectional link with very low power
Idiff = 0.2mA
Z0 = 100 W
Low Current Differential Signal
e.g.
80 MHz  12 pJ/bit
LCDS voltage swing  20mV
Conclusions
• Present CMS pixel system can be modifed with 0.13m technology to work < 4-5 x
1034
• Please think about cabling from the beginning  especially in view of triggering
 in view of assembly & cost
 in view of accessibility
• Trigger layers will be power hungry !
( CMS muon-pt should go to outer radius)
• Costing and affordability of SLHC tracker is crucial !  low cost design by us !
• Cooling is the dominant material budget driver !
 reduce power ! !
 low mass cooling possible ?
• Propose development of LCDS – bidirectional ohmic link with very little power !
Power Dissipation of Pixel ROC’s
• ROC architecture and designs have considerable influence on power dissipation
• 3 chips in same 0.25m technology for same LHC environment
Power/
chip
Power/
pixel
Power
density
[mW]
[mW]
[ mW/cm2 ]
300
810
99
466
35
75
190
67
335
32
24
121
29
194
87
21
142
# Pixels
/ chip
Pixel area
[mm2]
Idig
Iana
[mA]
[mA]
ALICE
8192
21’250
150
ATLAS
2880
20’000
CMS
4160
15’000
CMS no on-chip regulators