Transcript Chapter 3 Part 2 - Shift Registers

3.2 Shift Register
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Basic shift register function
Serial in / serial out shift registers
Serial in / parallel out shift registers
Parallel in / serial out shift registers
Parallel in / parallel out shift registers
Bidirectional shift registers
Shift register applications
Sequential Logic Circuits
Combinational
outputs
Memory outputs
Combinational
logic
Memory
elements
Inputs
Sequential circuit = Combinational logic + Memory Elements
Current State of A sequential Circuit:
Value stored in memory elements (value of state variables).
State transition:
A change in the stored values in memory elements thus changing
the sequential circuit from one state to another state.
Registers
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A register is a memory device that can be
used to store more than one-bit
information
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A register is usually realized as several
flip-flops with common control signals that
control the movement of data to and from
the register
Registers

An n-bit register is a collection of n D flip-flops
with a common clock used to store n related bits.
1D
74LS175
Q
D
CLR
2D
Q
Q
D
CLR
Q
1Q
Example:
74LS175 4-bit register
/1Q
2Q
74LS175
CLK
CLR
/2Q
1D
3D
Q
D
CLR
4D
CLK
/CLR
Q
Q
D
CLR
Q
3Q
/3Q
4Q
/4Q
2D
3D
4D
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
Shift Registers
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Multi-bit register that moves stored data bits
left/right ( 1 bit position per clock cycle)
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RSI
Shift Left is towards MSB
Q3 Q2 Q1
Q0
0
1
1
1
Q3 Q2 Q1
LSI
1
1
Q0
1 LSI
Shift Right (or Shift Up) is towards MSB
Q3 Q2 Q1
Q0
0
1
1
1
Q3 Q2 Q1
RSI
0
1
Q0
1
Basic Shift Register Functions
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Consist of an arrangement of flip-flops
Important in applications involving storage
and transfer of data (data movement) in
digital system
Used for storing and shifting data (1s and
0s) entered into it from an external source
and possesses no characteristic internal
sequence of states.
D flip-flops are use to store and move data
The flip-flop as a storage element
Still remember the truth table for D flip flop?
D
CLK/C
Q
Q’_________________
1
↑
1
0
SET (stores a 1)
0
↑
0
1
RESET (stores a 0)
The flip-flop as a storage element
When a 1 is on D, Q
becomes a 1 at
triggering edge of CLK or
remains a 1 if already in
the SET state
When a 0 is on D, Q
becomes a 0 at
triggering edge of CLK or
remains a 0 if already in
the RESET state
Types of Shift Register
1.
2.
3.
4.
Serial In / Serial Out Shift Registers
(SISO)
Serial In /Parallel Out Shift Registers
(SIPO)
Parallel In / Serial Out Shift Registers
(PISO)
Parallel In / Parallel Out Shift Registers
(PIPO)
Basic data movement in shift registers
(Four bits are used for illustration. The bits move in
the direction of the arrows.)
Serial In, Serial Out Shift Register
(SISO)
SRG n
SERIN
CLOCK
D
>
SI
Q
CLK
D
SO
For a n-bit SRG:
Serial Out = Serial In delayed by
n clock period
Q
CLK
4-bit shift register example:
serin: 1 0 1 1 0 0 1 1 1 0
serout: - - - - 1 0 1 1 0 0
clock:
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

D
CLK
Q
SEROUT
Serial In, Serial Out Shift Register
(SISO)
Serial In, Serial Out Shift Register
(SISO)
FF0
Clear
0
1010
0
101
0
10
1
1
0
Clear
1
FF1
0
0
0
0
1
0
FF2
0
0
0
0
0
1
FF3
0
0
0
0
0
0
0
00
000
0000
Serial In, Serial Out Shift Register
(SISO)
Clk
FF0
FF1
FF2
FF3
0
Clear
0
0
0
0
1
1011001110
0
0
0
0
2
101100111
0
0
0
0
3
10110011
1
0
0
0
4
1011001
1
1
0
0
5
101100
1
1
1
0
6
10110
0
1
1
1
0
7
1011
0
0
1
1
10
8
101
1
0
0
1
110
9
10
1
1
0
0
1110
10
1
0
1
1
0
01110
11
Clear
1
0
1
1
001110
Serial In, Serial Out Shift Register
(SISO)
FF0
FF1
FF2
FF3
Clear
0
0
0
0
1011001110
0
0
0
0
101100111
0
0
0
0
10110011
1
0
0
0
1011001
1
1
0
0
101100
1
1
1
0
10110
0
1
1
1
0
1011
0
0
1
1
10
101
1
0
0
1
110
10
1
1
0
0
1110
1
0
1
1
0
01110
Clear
1
0
1
1
001110
Serial In, Serial Out Shift Register (SISO)
Serial In, Parallel Out Shift register
(SIPO)
SERIN
CLOCK
D
Q
1Q
CLK
D
Q
2Q
CLK
CLK
>
SI
1Q
2Q



nQ
(SO)
Serial to Parallel Converter
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
D
SRG n
Q
nQ
Example: 4-bit shift register
serin: 1 0 1 1 0 0 1 1 1 0
1Q:
- 101100111
2Q:
- - 10110011
3Q:
- - - 1011001
4Q:
- - - - 101100
clock:
Can u see the difference?
SERIN
CLOCK
D
Q
1Q
CLOCK
CLK
D
SERIN
Q
2Q
D
Q
CLK
D
Q
CLK
CLK






D
CLK
Q
nQ
D
CLK
Q
SEROUT
Serial In, Parallel Out Shift register (SIPO)
• Data bits entered serially (right-most bit first)
• Difference from SISO is the way data bits are taken
out of the register – in parallel.
• Output of each stage is available
Example :
The states of 4-bit register (SRG 4) for the data input and
clocks waveforms.
Assume the register initially contains all 1s
4-bit parallel in/serial out shift register (PISO)
4-bit parallel in/serial out shift register (PISO)
When signal = 1,
SHIFT
When signal = 0,
 LOAD
4-bit parallel in/serial out shift register (PISO)
When signal = 0,
LOAD
G1 – G3
enabled
4-bit parallel in/serial out shift register (PISO)
When signal = 1,
SHIFT
G4 – G6
enabled
4-bit parallel in/serial out shift register (PISO)
Can you try and trace the output for each FF stage
until you get Q3?
Let’s try to trace this one first…
1
0
1
Assume that the
signal has
values
011011 for 6
respective clock
cycle
For the parallel data input
Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0
0
Let’s try to trace this one first…
0
1
0
1
0
1
0
CLK 1,
Signal = 0
G1 – G3
Will get value = 1
G4 – G6
Will get value = 0
Referring to the AND gate theory,
All gates that receives “0” values at shift/load can be ignored.
Let’s try to trace this one first…
1
1
0
1
1
1
Now, AND the shift/load with respective Data bit, D0 – D3
0
Let’s try to trace this one first…
1
0
0
1
0
1
1
CLK 2,
Signal = 1
G1 – G3
Will get value = 0
1
0
1
0
G4 – G6
Will get value = 1
Referring to the AND gate theory,
All gates that receives “0” values at shift/load can be ignored.
Let’s try to trace this one first…
1
1
1
0
1
1
Now, AND the shift/load value with
Respective data that goes into G4, G5, G6
0
How do you put it in table?
For the parallel data input
Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0
Clk Shift/Load
Active
signal
Q0
Q1
Q2
Q3
0
Clear
Clear
0
0
0
0
1
0
LOAD
1
0
1
0
2
1
SHIFT
1
1
0
1
3
1
SHIFT
1
1
1
0
4
0
LOAD
1
0
1
0
5
1
SHIFT
1
1
0
1
6
1
SHIFT
1
1
1
0
Can you try and trace the output for each FF stage
until you get Q3?
Parallel In, Serial Out Shift Register (PISO)
CLOCK
LOAD/SHIFT
SERIN
1D
1Q
S
D
L
CLK
2Q
S
2D
Q
D
L
Q
CLK
Parallel to Serial
Converter



Load/Shift=1
Di Qi
Load/Shift=0
Qi Qi+1
S
ND
L



NQ
D
CLK
Q
SEROUT
Parallel In, Parallel Out Shift Register (PIPO)
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Immediately following simultaneous entry of all data bits,
it appear on parallel output.
Parallel In, Parallel Out Shift Register (PIPO)
CLOCK
LOAD/SHIFT
SERIN
1D
S
D
L
L
Q
2Q
Q
NQ
CLK



S
ND
D
L
General Purpose:
Makes any kind of
(left) shift register
1Q
CLK
S
2D
Q



D
CLK
Parallel In, Parallel Out Shift Register
(PIPO)
Bi-directional Shift Registers
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Data can be shifted left
Data can be shifted right
A parallel load maybe possible
74HC194 is a bidirectional universal shift
register
Bi-directional Universal Shift Registers
11
1
Modes:
Hold
Load
Shift Right
Shift Left
10
9
7
6
5
4
3
2
CLK
CLR
S1
S0
LIN
D
C
B
A
RIN
74x194
R
QD
QC
QB
QA
L
12
13
14
15
4-bit Bi-directional Universal (4-bit) PIPO
Function
Hold
Shift right/up
Shift left/down
Load
Mode
S1 S0
0
0
0
1
1
0
1
1
Next state
QA* QB* QC*
QA QB QC
RIN QA QB
QB QC QD
A
B
C
QD*
QD
QC
LIN
D
Four-bit Johnson counters
Serial output
connected back
toserial input
The complement
of the output (Q’)
is fedback into
1st FF.
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Five-bit Johnson counters
A 10-bit ring counter
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Assume initial state : 0000000101
Shift Register Applications
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State Registers
 Shift registers are often used as the state register in a
sequential device. Usually, the next state is
determined by shifting right and inserting a primary
input or output into the next position (i.e. a finite
memory machine)
 Very effective for sequence detectors
Serial Interconnection of Systems
 keep interconnection cost low with serial interconnect
Shift Register Applications
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Bit Serial Operations
 Bit serial operations can be performed quickly through
device iteration
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Iteration (a purely combinational approach) is
expensive (in terms of # of transistors, chip area,
power, etc).
A sequential approach allows the reuse of
combinational functional units throughout the multicycle operation
Shift Register Applications Example:
Serial Interconnection of Systems
CLOCK
Transmitter
Control
Circuits
Parallel
Data from
A-to-D
converter
n
Parallelto-serial
converter
Control
/SYNC
Receiver
Circuits
Serial DATA
One bit
Serial-toparallel
converter
Parallel
Data to
D-to-A
converter
n
Shift Register Applications Example:
The shift register as a time-delay device