Transcript Total Ionizing Dose Effects in Silicon Technologies and Devices

MURI
Total Ionizing Dose Effects in
Silicon Technologies and Devices
Hugh Barnaby, Philippe Adell*, Jie Chen,
Michael Mclain, Ivan Sanchez, Harshit Shah
Arizona State University
*Jet Propulsion Laboratory
Topics
 Modeling total ionizing dose effects in deep submicron bulk
CMOS technologies
- Hugh Barnaby, ASU
 Band-to-band tunneling (BBT) induced leakage current
enhancement in irradiated fully depleted SOI devices
- Philippe Adell, JPL
 Mechanisms of enhanced radiation-induced degradation due
to excess molecular hydrogen in bipolar oxides
- Jie Chen, ASU
MURI
Modeling Total Ionizing Dose
Effects in Deep Submicron Bulk
CMOS technologies
Hugh Barnaby, Michael Mclain, Ivan Sanchez,
Harshit Shah
Department of Electrical Engineering
Ira A. Fulton School of Engineering
Arizona State University
ASU task
• Characterize and model TID effects in bulk deep
submicron CMOS devices
• Design and build radiation-enabled compact
models
• Technologies: deep sub-micron bulk CMOS,
silicon on insulator, device isolation structures
(STI, BOX)
Reliability threats
•
3
Supply Voltage (V)
Hot Carrier Limit Region
•
250nm
ITRS Roadmap
2
180nm
•
130nm
NBTI Limit Region
Traditional:
Hot-Carrier-Injection
(HCI)
Nanoscale roadblock:
Negative-biastemperature-instability
(NBTI)
Other issues:
TDDB, etc.
1
2
3
4
Oxide Thickness (nm)
5
after N. Kimizuka et al., VLSI
Tech. 1999
Radiation threats in bulk CMOS
n+
n+
n+
n+
Poly
gate
Poly
gate
Aluminum line
Radiation damage in shallow trench oxides increases
leakage
Intra-device leakage
Inter-device leakage
0V
n+
n+
Aluminum gate
+
+
+
+
+++++++++++++
VDD
n+
Leakage path
1.0E-03
1.E-01
FOX Drain Current (A)
1.0E-04
Drain Current (A)
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
Increased total dose
1.0E-10
1.0E-11
NMOS 0.16/0.12
1.0E-12
-0.2
0.3
0.8
Gate Voltage (V)
after Faccio et al., TNS 2005
1.3
1.E-02
1.E-03
1.E-04
1.E-05
1.E-06
1.E-07
1.E-08
1.E-09
1.E-10
1.E-11
1.E-12
Increased total dose
1.E-13
-10 -2 7 16 24 33 41 50 58 67 75 84 92
FOX Gate Voltage (V)
n+
TID Defects
Defects
> 300 nm
• Not - oxide trapped charge (E’ )
• Nit – interface traps (Pb)
STI
Gate oxide < 3 nm
n+ drain
n+ source
STI
halo implants
Both Nit and Not are related to holes
generated and/or hydrogen present in
oxide
first order
assumption
Not, Nit a tox
Trapped charge
buildupp-body
in STI
Research Goal
To develop a compact modeling approach that can
simulate and predict the effects of stress and radiation
damage of semiconductor devices and circuits?
Research Goal
To develop a compact modeling approach that can
simulate and predict the effects of stress and radiation
damage of semiconductor devices and circuits?
This capability, known as Predictive Technology
Modeling (PTM), has been demonstrated for
modeling negative bias temperature instability.
Predictive technology
modeling (PTM)
The goal of PTM is to develop compact
modeling approaches that are:
• Scalable with technology and design parameters
• Capable of both short-term and long-term predictions
• Compatible with standard circuit simulator
• Extendable to emerging reliability and radiation
effects concerns
PTM Approach (for NBTI)
Experimental Data
Transistors
Model validation path
Device
comparison
Technology Parameters
- material (eX)
VLSI Circuit Simulation
- device (fms, tox, Nx)
- other structural features
(e.g. trench aspect ratio)
Stress Model
DNit = Ktn + d
Defect Densities
Stress Parameters
Device I-V sim
0
1
Compact Model
Nit
static, dynamic
A, E0, EA
External Conditions
- Bias
- Temperature
Device Layout
- Time
- gate geometry (W, L)
Modeling inputs
Circuit simulation
with ageing effects
Model validation

Model verified with published silicon data
Tox=2nm
Tox=3nm
Tox=2.6nm, T=125oC
Vgs=2.9V, T=100oC
Tox=4nm
DVth (mV)
DVth (mV)
Model
10
1
,
10
3
10
4
10
Time (s)
180nm, VLSI, 1999

0.1
,
Eox=9.1, 8.0, 6.9, 5.7MV/cm
Model
n=0.25
2
,
0.1
1
Time (s)
10
130nm, IRPS, 2003
Excellent scalability over process and design conditions
After Vattikonda et al. DAC 2006.
Research Goal
To develop a compact modeling approach that can
simulate and predict the effects of stress and radiation
damage of semiconductor devices and circuits?
This capability, known as Predictive Technology
Modeling (PTM) has already been demonstrated for
modeling negative bias temperature instability at ASU.
Our goal is to extend PTM for reliability to capture
radiation effects
PTM Approach (for TID)
Device
comparison
Technology Parameters
Experimental Data
Transistors
- material (eX)
- device (fms, tox, Nx)
- other structural features
(e.g. trench aspect ratio)
Radiation Source
Input Parameters
Compact Model
Radiation Model
- Dose (D), Dose rate (D’)
- Radiation source (e.g Co60)
- Vth modeling approach
DNot = Dkgfyfottox
DNit = DkgfyfDHfittox - x
Defect Densities
Not, Nit
External Conditions
- Bias
VLSI Circuit Simulation
- BSIM3/4
- industry standard thru 2006
Radiation Dose Model Parameters
- PSP
- new industry standard beyond
2006
- surface potential modeling
approach
Device I-V sim
0
1
static, dynamic
Key Compact Model Parameters
kg, fDH, fit, fy, fot
Weff (STI), toxeff (STI), CIT, Vth0
(BSIM), fs (PSP)
- Temperature
- Packaging
Device Layout
- gate geometry (W, L)
- RHBD design
- Antenna effects
Experimental Data
Specialized Structures
Structure
comparison
Modeling
inputs
Technology Computer
Aided Design
Radiation-enabled
circuit simulation
Radiation-enabled PTM
(Physical Module)
Inputs
Technology Parameters
Physical
Module
Output
(defects)
- material (eX)
- device (fms, tox, Nx)
- other structural features
(e.g. trench aspect ratio)
Radiation Model
External Conditions
- Bias
- Temperature
DNot = Dkgfyfottox
- Packaging
DNit = DkgfyfDHfittox - x
Defect Densities
Not, Nit
Radiation Source
Input Parameters
Radiation Dose Model Parameters
kg, fDH, fit, fy, fot
- Dose (D), Dose rate (D’)
- Radiation source (e.g Co60)
Device Layout
- gate geometry (W, L)
- RHBD design
- Antenna effects
Experimental Data
Specialized Structures
Structure
comparison
Model validation
Technology Computer
Aided Design
Closed form model for TID

Oxide trapped charge dependence on dose, oxide field and thickness.


ΔN ot x   Dk g f y ε  f ot ε tox x 

Interface trap dependence on dose, oxide field and thickness.

ΔN it  Dk g f y ε  f DH f it tox
Model Parameters
D
- total dose [rad]
kg
- 8.1 x 1012 [ehp/radcm3]
fy
- field dependent hole yield [hole/ehp]
fot
- trapping efficiency [trapped hole/hole]
Models based on
assumptions of
steady state, unidirectional flux, and
no saturation or
annealing
fDH - hole, D’H reaction efficiency [H+/hole]
fit
- H+, SiH de-passivation efficiency [interface trap/H+]
tox
- oxide thickness [cm]
See Barnaby, MURI presentation 2006
Simple Model – Not(x)
Vg
The simple model requires:
1.
Doping distribution along sidewall to
generate NA(i) and fMS(i) arrays
2.
Field line estimates to generate
tox(i) and eox(i) arrays
3.
eox(i)
x(i)
NA(i)
+
+
x
(i+1)
Vgb bias condition
STI
… to compute the e-field.
Vb
Surface potential
x
E-field a function
of Not (iterative)
Vgb  fms i   s i  qN ot xi 
e ox i  

tox i 
ox

Non-uniform doping
Sidewall
doping
In deep submicron CMOS,
the doping along the
sidewall is highly non-uniform
TCAD Modeling
TCAD modeling with the Silvaco REM simulator can generate volumetric
distributions of trapped charge in the STI (for model validation).
1 krad
10 krad
100 krad
Not estimates
Vgb = 1V
100 krad
10 krad
Vgb = 0V
10krad dose
1 krad
Vgb = 0V
Simulator predicts dose and bias dependence (as well as temperature,
dose rate, etc.).
Radiation-enabled PTM
(Compact modeling)
to phys. mod.
Device
comparison
Experimental Data
Transistors
Model validation
Nit, Not
from phys.
mod.
Device I-V sim
Compact Model
static, dynamic
Technology Parameters
- material (eX)
- device (fms, tox, Nx)
- other structural features
(e.g. trench aspect ratio)
to circuit sim.
External Conditions
Device Layout
- Bias
- gate geometry (W, L)
- Temperature
- RHBD
- Time
- Packaging
Compact Modeling for TID
(surface potential)
 s  x, y   VG  VFB x, s x, y   Qs  x, s  x, y 
Nit, Not
from phys.
mod.
qN  x  qN it
VFB x, s x, y   VFB0  x   ot 
Cox  x 
Qs  x, s  x, y    x   s  x, y   ft
ni
x, s x, y 
Cox  x 
charged
2
N A x 
2
e
  s  x , y V  y  


ft


Surface potential information is used in the PSP compact
model being developed and refined at ASU.
s(x,y)
Compact Modeling for TID
(drain-source leakage)
Poly Gate
N+ source
MA.D.
MR1
eff
I D ,drift Depth

L
of halo
~25 um (MR1)
+
++
++
+
STI
MR2
 s  x,L 
xd
  
0
s
Depth
of D/S diff
~50 um (MR2)
MR2
I D ,diff  
eff
L
x,0 
Qi   x, y d s dx
MR1
xd
 
0
Qi  s  x , L 
Qi  s  x , 0 
dQi   x, y dx
STI
N+ drain
Poly Gate
Effect of charge buildup along STI sidewall degrades can be modeled
as two parasitic nMOSFETs (MR1 and MR2) operating in parallel with as
drawn device, MA.D.
D-S leakage model using
BSIM4 compact model
-0.5
-0.3
-0.1
0.1
0.3
0.5
0.7
0.9
1.E-03
1.E-04
MA.D.
1.E-05
MR1
MR2
MR1
1.E-06
1.E-07
MR2
Parameters in modified BSIM4 model enables
parasitic devices to be modeled
1.E-08
1.E-09
1.E-10
MA.D.
model nfetMR1_10MRAD bsim4 type=n (W=50.1nm L=120nm)
+ tnom = 27
toxe = 12.46e-009 toxp = 1.1e-9
+ rnoia = 0.577
rnoib = 0.37 vth0 = 0.20439
+ cdsc = 0
cdscb = 0 cdscd = 0 cit = -0.00161
+ + u0
= 0.026 ua = 1e-10 ub = 4e-16
+ ……
Modeling bias dependence with
BSIM4
-0.25
0
0.25
0.5
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
1.0E-10
1.0E-11
Id data pre
Id sim pre
Id data T1
Id sim T1
Id data T2
Id sim T2
Id data T3
Id sim T3
Circuit Level Modeling
(A/D Converter)
Flash-type
ADC
• Compact (C-) models, degraded
as function of dose and
radiation bias, are used by
EDA tools to model circuit
degradation over time.
• C-models can be inserted at the
circuit-level (SPICE/SPECTRE)
or in higher level behavioral
models for increased efficiency.
Circuit Level Modeling
(results)
Modeled application response to intra-device leakage under
static radiation bias conditions
SMASH 5.2.2 - Transient C:\EskoMikkola\Engineering\FALL2005\AMS\BLOCKS7\4bit_adc_tid.NSX - Tue Jan 31 12:49:40 2006
= 10.46mHz, slope = 0.015
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
180
190
200
210
1.6V
Missing
code
1.2V
800mV
400mV
Output
0V
2V
Input voltage
1.6V
1.2V
800mV
400mV
0V
500K
400K
Radiation dose
300K
200K
100K
0
after Mikkola et al. RADECS 2006