Transcript 2.7 MB PowerPoint

Digital Guitar Recorder
Team RAD –
Michael McGuirk
Fish Abrhaley
David Wormus
Nick Herrera
Primary Project Objectives
• Record analog guitar waveform to
Compact Flash solid state memory
• Add Fuzz, Octave, and Tremolo effects
• Utilize Xilinx XCV1000 FPGA for
processing needs and control of
peripheral logic
• Ability to store multiple track files, files
stored in WAV format
Analog Guitar to Digital Data
• Guitar Input is 0 to 1V
p-p, average 200 mVp-p
• Then 3 effects in series,
with bypass switches
• Next, Negative
Feedback OpAmp gain
of 3
• A/D is expecting 3V
logical high, 0V low and
is controlled by main
controller
• 8-bit data passed to
FIFO and WAV
formatter
Distortion
Distortion Effect
• Signal is clipped from both the top and
bottom, effectively adding higher
frequency harmonics.
• The two voltage levels at which the
signal is clipped are fixed. To increase
distortion, the input signal is amplified,
leading to more distortion but also to
higher volume (increased RMS value).
Octave Up
Octave effects
• The input signal is first
passed through a full
wave rectifier creating
the following signal
• Lowpass filter to
“smooth out” sharp
edges, effectively
creating DC-biased
sinusoid
• High-pass filter with
cutoff frequency < 80
Hz eliminating the DCbias of the signal
Tremolo
A/D Converter
Compact Flash Controller
•
•
•
•
Reads 8-bit parallel data from
A/D converter from FIFO
Adds WAV file header to data
Reads File Format Boot Sector
and writes data into FAT16 file
structure
Performs read and write
transaction to and from CF card
conforming to timing and
electrical specification.
WAV File Format
Header contents of WAV file.
Number of bytes recorded
needs to be counted and
added to first 40 bytes of file
cluster.
FAT 16 File System
Memory structure of a FAT16 volume
Partition Boot Sector Description
FAT - File Allocation Table - Identifies each cluster on disk as:
•
•
•
•
Unused
In use by file
Bad cluster
Last cluster in a file
Compact Flash Control
Control line descriptions of Compact Flash
read and write for 8-bit memory and
register access
Compact Flash Memory
Transaction Timing
Common Memory Write
Common Memory Read
Main Controller
• Receives and
issues control
signals to all
functional blocks
• Accepts input from
user interface
• Implemented
using soft
processor core or
VHDL
Inside the FPGA
• Implemented using VHDL in Xilinx ISE
5.1i
FPGA Pinouts
Top Level
• Ties together all submodules
• ADC/DAC, LCD, Flash and main controllers
• Recording and Playback FIFO’s
• Clock divider and debounce modules
ADC Controller
ADC Controller Logic
ADC Controller/FIFO Simulation
Main Controller
• Simple state machine
• Init, Record, stop record, play, stop play
and change track
• Handles all handshaking between modules
Controller Signals
Controller Logic
Controller Simulation
Recording/Playback FIFO’s
• Used Xilinx Asynchronous FIFO Core
• Acts as buffer between clock domains
• Customized using Xilinx Core Generator
• Utilizes Virtex Block Memory
• CoreGen Outputs an EDIF Netlist
Core Generator GUI
Asynchronous FIFO Logic
LCD Controller
• State Machine handles writing to LCD
based on inputs from controller
LCD Module Pin Assignments
PIN #
1
2
3
4
PIN
Vss
Vcc
VL
RS
5 R/W
6
7
8
9
10
11
12
13
14
E
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Description
Power Supply Neg
Power Supply Pos
Contrast Adjust
H:when reading/writing
L:when initializing
H: Data Read from LCD
L: Data Write to LCD
Chip Enable
Data bus line 0 (LSB)
Data bus line 1
Data bus line 2
Data bus line 3
Data bus line 4
Data bus line 5
Data bus line 6
Data bus line 7 (MSB)
Input
Ground
+ 3.3V
N.C.
from FPGA
H (3.3V) during op
Ground
for Writing
H (+3.3V)
Write Data and Initilization
Write Data and Initilization
Write Data and Initilization
Write Data and Initilization
Write Data and Initilization
Write Data and Initilization
Write Data and Initilization
Write Data and Initilization
Module is a PCB with 14 pin-holes for soldering leads on
one side, and the LCD screen on the other
LCD Addressing & Initialization
• Displaying Characters on 2x8:
• Controller sets RS (pin 4) HI and put hex
on data pins
Character Position(dec)-->
00
01
02
03
04
05
06
07
Row 0 DDRAM Address (hex)-->
00h
01h
02h
03h
04h
05h
06h
07h
Row 1 DDRAM Address (hex) -->
08h
09h
0A
0B
0C
0D
0E
0F
• Initializing the LCD Module
• With RS = LOW, HI/LOW on different data pins
can change things like cursor position and blink
on/off, and set up an 8-bit interface.
User Interface/LCD
• 5-way button for
Record, Play,Stop, Track
Select, ON/OFF
• 8x2 character LCD
displays current mode
(play etc.) and track
numbers.
• LCD controller is on
FPGA written in VHDL
Digital Playback and Analog
Output
• Data is buffered from
FIFO into D/A during
playback off of C.F.
• Simultaneous output
from guitarout and
D/Aout.
• Audio amplifier is
transistor based, have
not researched yet.
DAC AD5330 TSSOP
High-level Project
Implementation
Schedule
Milestones
• Milestone 1 - 3/16/04
• ADC to FIFO to DAC
• Compact Flash Write and
Read on Hardware
• Compact Flash Controller
Simulated
• LCD Controller Simulated
• Analog effects built and
tested
• Milestone 2 – 4/6/04
• All system modules
coded/built to test and
debug stage
BOM
Parts and Cost
Parts name
Price
Compact flash (16Mbyte)
$0( donated)
Compact flash Printed circuit board
$40.00
Operational amplifiers
$0.50
Assorted Transistors & Resistors
$10.00
DAC ( sample)
$0
ADC (sample)
$0.00
Compact flash connector
$8.00
DAC SSOP (pcb)
$10.00
LCD
$11.00
Perforated Proto board
$11.00
quantity total cost
2
1
5
1
1
1
1
1
$0.00
$40.00
$2.50
$10.00
$0.00
$0.00
$8.00
$10.00
$11.00
$11.00
$92.50
QUESTIONS
A Team Rad Production