Transcript Intel-Pentium-Series-by-Tim-Barto-2002-SUMMER-CS

The Pentium Series
CS 585: Computer Architecture
Summer 2002
Tim Barto
Purpose of Presentation
• Give brief overview of Pentium Series line of
processors
• Describe caching scheme used in the Pentium
Processor
• Structure
• Operating modes
• Techniques to maintain consistency
• Describe integer pipelines and instruction flow
Summary of the Pentium Series of Processors
Pentium
Processor
Introduced
Operations Per
Clock Cycle
Max Clock
Speed
Bus Frequency
Number of
Transistors
Pentium Pro
Processor
Pentium II
Processor
Pentium III
Processor
Pentium 4
Processor
03/23/93
11/01/95
05/07/97
02/26/99
11/20/00
2
3
3
5
6
60MHz system
bus:
60MHz system
bus:
66MHz system
bus:
100MHz system
bus:
400MHz system
bus:
150MHz
180MHz
333MHz
1.0GHz
2.40GHz
66MHz system
bus:
66MHz system
bus:
100MHz system
bus:
133MHz system
bus:
533MHz system
bus:
200MHz
200MHz
450MHz
1.4GHz
2.53GHz
60MHz,
66MHz
60MHz,
66MHz
66MHz,
100MHz
100MHz,
133MHz
400MHz
(100 * 4),
533MHz
(133 * 4)
3,100,000
(0.8 micron)
5,500,000
(0.35 micron)
7,500,000
(0.35 micron)
24,000,000
(0.13 micron)
42,000,000
(0.13 micron)
Summary of the Pentium Series of Processors (continued)
Pentium
Processor
Pentium Pro
Processor
Pentium II
Processor
Pentium III
Processor
Pentium 4
Processor
L1 Cache
16KB
16KB
32KB
32KB
12k µop + 8KB
Data
L2 Cache
-
1MB
(on chip)
512KB
(off chip)
512KB
(on chip)
512KB
(on chip)
4GB
64GB
64GB
64GB
64GB
Integer
Pipelines
2
2
2
2
4
Floating Point
Pipelines
1
1
1
1
2
Intel’s first true
server /
workstation
chip
Dual independent
bus, dynamic
execution, Intel
MMX technology
Addressable
Memory
Brief
Description
Superscalar
architecture
brought 5X the
performance of
the 33MHz
Intel486 DX
processor
Data Prefetch
Logic, Level 2
Advanced
Transfer Cache
Capable of
delivering 4.2GB
of data-persecond into and
out of the
processor
Pentium Processor
• Successor to the Intel486 processor
• 16-bit based
• Originally introduced with a 60MHz clock speed
• Added a second execution pipeline to achieve twoway superscalar performance
• CISC instruction set
Cache Structure
• Has only one level of on-chip cache, L1
• L1 size = 16KB
• Divided into two 8KB sections (one for code the other
for data)
• Organized in a set-associative structure
Cache Operation Modes
• Two bits which allow for control of cache:
• CD (Cache Disable)
• NW (Not Write-Through)
• CD = 1, disables cache
• CD = 0, enables cache
• NW = 1, enables write-back mode
• NW = 0, enables write-through mode
Cache Consistency
• Data cache uses the MESI Protocol
• M (Modified) state indicates line is modified
• E (Exclusive) state indicates line is not modified
• S (Shared) state indicates line may be shared with
other caches
•I (Invalid) state indicates line is not available in
cache
• Code cache uses a subset of MESI Protocol
• Supports S (Shared) and I (Invalid) states
Cache Consistency (continued)
Additional methods used to ensure cache consistency:
• Inquire Cycles
• Cache Flushing
Integer Pipelines and Instruction Flow
• Uses two parallel pipelines known as “U” and
“V” pipes
• U pipe has 5 stages
• Prefetch (PF)
• Instruction Decode (D1)
• Address Generate (D2)
• Execute (E)
• Writeback (WB)
Integer Pipelines and Instruction Flow (continued)
• V pipe is similar to the U pipe but has some
limitations on the instructions it can execute
Conclusion
• Pentium processor successfully expanded upon
the Intel486’s architecture
• Today, the Pentium 4 continues to break new
ground in processor technology
• For more information, check out:
http://www.intel.com/design/pentium/manuals/