Transcript Syllabus

Computer Organization
Lecture 1
Course Introduction
and the
Five Components of a Computer
Modified From the Lectures of Randy H. Katz
UC Berkeley
CS152 / Fall 2002
Lec 1.1
Lecture Overview
 Intro to Computer Architecture (30 minutes)
 Administrative Matters (5 minutes)
 Course Style, Philosophy and Structure (15 min)
 Break (5 min)
 Organization and Anatomy of a Computer (25 min)
Lec 1.2
What is “Computer Architecture”?
Computer Architecture =
 Instruction Set Architecture +
 Machine Organization + …
Lec 1.3
Instruction Set Architecture
(subset of Computer Architecture)
“... the attributes of a [computing] system as seen by
the programmer, i.e., the conceptual structure and
functional behavior, as distinct from the organization
of the data flows and controls the logic design, and the
physical implementation.”
– Amdahl, Blaaw, and Brooks, 1964
• Organization of Programmable Storage
SOFTWARE
• Data Types & Data Structures:
Encodings & Representations
• Instruction Set
• Instruction Formats
• Modes of Addressing and Accessing Data Items and Instructions
• Exceptional Conditions
Lec 1.4
Computer Architecture’s Changing Definition
 1950s to 1960s Computer Architecture Course
• Computer Arithmetic
 1970s to mid 1980s Computer Architecture Course
• Instruction Set Design, especially ISA appropriate for
compilers
 1990s Computer Architecture Course
• Design of CPU, memory system, I/O system, Multiprocessors, Networks
 2000s Computer Architecture Course:
• Special purpose architectures, Functionally reconfigurable,
Special considerations for low power/mobile processing
Lec 1.5
The Instruction Set: a Critical Interface
software
instruction set
hardware
Lec 1.6
Example ISAs (Instruction Set Architectures)
 Digital Alpha
(v1, v3)
1992-97
 HP PA-RISC
(v1.1, v2.0)
1986-96
 Sun Sparc
(v8, v9)
1987-95
 SGI MIPS
(MIPS I, II, III, IV, V)
1986-96
 Intel
(8086,80286,80386,
80486,Pentium, MMX, ...)
Itanium/I64
1978-00
2002-
Lec 1.7
MIPS R3000 Instruction Set Architecture
(Summary)
 Instruction Categories
Registers
• Load/Store
R0 - R31
• Computational
• Jump and Branch
• Floating Point
-
PC
HI
coprocessor
• Memory Management
LO
• Special
3 Instruction Formats: all 32 bits wide
OP
rs
rt
OP
rs
rt
OP
rd
sa
funct
immediate
jump target
Q: How many already familiar with MIPS ISA?
Lec 1.8
Organization
 Capabilities & performance characteristics
of principal functional units
• (e.g., Registers, ALU, Shifters,
Logic Units, ...)
 Ways in which these components are
interconnected
Logic Designer's View
ISA Level
FUs & Interconnect
 Information flows between components
 Logic and means by which such
information flow is controlled
 Choreography of FUs to realize the ISA
 Register Transfer Level (RTL) Description
Lec 1.9
The Big Picture
 Since 1946 all computers have had 5 components
Processor
Input
Control
Memory
Datapath
Output
Lec 1.10
Example Organization
 TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20
MBus Module
SuperSPARC
Floating-point Unit
L2
$
Integer Unit
Inst
Cache
Ref
MMU
Data
Cache
CC
MBus
L64852 MBus control
M-S Adapter
SBus
Store
Buffer
Bus Interface
DRAM
Controller
SBus
DMA
SBus
Cards
SCSI
Ethernet
STDIO
serial
kbd
mouse
audio
RTC
Boot PROM
Floppy
Lec 1.11
What is “Computer Architecture”?
Application
Operating
System
Compiler
Firmware
Instr. Set Proc. I/O system
Instruction Set
Architecture
Datapath & Control
Digital Design
Circuit Design
Layout
 Coordination of many levels of abstraction
 Under a rapidly changing set of forces
 Design, Measurement, and Evaluation
Lec 1.12
Forces on Computer Architecture
Technology
Programming
Languages
Applications
Computer
Architecture
Operating
Systems
Cleverness
History
Lec 1.13
Technology
DRAM chip capacity
Microprocessor Logic Density
DRAM
Year
Size
1980
64 Kb
1983
100000000
10000000
R10000
Pentium
R4400
256 Kb
i80486
1986
1 Mb
1989
4 Mb
1992
16 Mb
Transistors
1000000
uP-Name
i80286
100000
R3010
i8086
1996
64 Mb
1999
256 Mb
2002
1 Gb
i80386
SU MIPS
i80x86
M68K
10000
MIPS
Alpha
i4004
1000
1965
1970
1975
1980
1985
1990
1995
2000
2005
 In ~1985 the single-chip processor (32-bit) and the singleboard computer emerged
• workstations, personal computers, multiprocessors have been
riding this wave since
 In the 2002+ timeframe, these may well look like mainframes
compared to single-chip computers (maybe 2 chips)
Lec 1.14
Technology Trends Imply Dramatic Change
 Processor
• Logic capacity:
about 30% per year
• Clock rate:
about 20% per year
 Memory
• DRAM capacity: about 60% per year (4x every 3 years)
• Memory speed:
about 10% per year
• Cost per bit:
improves about 25% per year
 Disk
• Capacity:
about 60% per year
• Total data use:
100% per 9 months!
 Network Bandwidth
• Bandwidth increasing more than 100% per year!
Lec 1.15
Log of Performance
Performance Trends
Supercomputers
Mainframes
Minicomputers
Microprocessors
Year
1970
1975
1980
1985
1990
1995
Lec 1.16
Applications and Languages
 CAD, CAM, CAE, . . .
 Lotus, DOS, . . .
 Multimedia, . . .
 The Web, . . .
 JAVA, . . .
 The Net => ubiquitous computing
 ???
Lec 1.17
Computers in the News: Sony Playstation 2000
 As reported in Microprocessor Report, Vol 13, No. 5:
• Emotion Engine: 6.2 GFLOPS, 75 million polygons per second
• Graphics Synthesizer: 2.4 Billion pixels per second
• Claim: Toy Story realism brought to games!
Lec 1.18
Where are We Going??
Input
Multiplier
Input
Multiplicand
32
Multiplicand
Register
LoadMp
32=>34
signEx
32
34
34
32=>34
signEx
1
0
34x2 MUX
Arithmetic
Multi x2/x1
34
34
Sub/Add
34-bit ALU
Control
Logic
34
32
32
2
ShiftAll
LO register
(16x2 bits)
Prev
2
Booth
Encoder
HI register
(16x2 bits)
LO[1]
Extra
2 bits
2
"LO
[0]"
Single/multicycle
Datapaths
<<1
ENC[2]
ENC[1]
ENC[0]
LoadLO
ClearHI
LoadHI
2
32
Result[HI]
LO[1:0]
32
Result[LO]
1000
CPU
“Moore’s Law”
IFetchDcd
WB
Exec Mem
Performance
10
DRAM
9%/yr.
DRAM (2X/10 yrs)
1
198
2
3
198
498
1
5
198
6
198
7
198
8
198
9
199
0
199
199
2
199
399
1
4
199
5
199
699
1
7
199
8
199
9
200
0
Exec Mem
Processor-Memory
Performance Gap:
(grows 50% / year)
198
098
1
1
198
IFetchDcd
CS152
Fall ’02
100
µProc
60%/yr.
(2X/1.5yr)
WB
Time
IFetchDcd
Exec Mem
IFetchDcd
WB
Exec Mem
WB
Pipelining
I/O
Lec 1.19
Memory Systems

CS152: Course Content
Computer Architecture and Engineering
Instruction Set Design
Computer Organization
Interfaces
Hardware Components
Compiler/System View
Logic Designer’s View
“Building Architect”
“Construction Engineer”
Lec 1.20
CS 152: So What's In It For Me?
 In-depth understanding of the inner-workings of
modern computers, their evolution, and trade-offs
present at the hardware/software boundary.
• Insight into fast/slow operations that are easy/hard to
implementation hardware
• Out-of-order execution and branch prediction
 Experience with the design process in the context of
a large complex (hardware) design.
• Functional Spec --> Control & Datapath --> Physical
implementation
• Modern CAD tools
 Designer's "Conceptual" toolbox
Lec 1.21
Conceptual Tool Box?
 Evaluation Techniques
 Levels of translation (e.g., Compilation)
 Levels of Interpretation (e.g., Microprogramming)
 Hierarchy (e.g, registers, cache, mem, disk,tape)
 Pipelining and Parallelism
 Static / Dynamic Scheduling
 Indirection and Address Translation
 Synchronous and Asynchronous Control Transfer
 Timing, Clocking, and Latching
 CAD Programs, Hardware Description Languages, Simulation
 Physical Building Blocks (e.g., CLA)
 Understanding Technology Trends
Lec 1.22
Course Structure
Design Intensive Class --- 100 hours per semester per student
MIPS Instruction Set ---> Standard-Cell implementation
Modern CAD System :
Schematic capture and Simulation
Design Description
Computer-based "breadboard"
• Behavior over time
• Before construction
 Lectures (rough breakdown):
•
•
•
•
•
•
Review: 2 weeks on ISA, arithmetic
1 1/2 weeks on technology, HDL, and arithmetic
3 1/2 weeks on standard proc. design and pipelining
2 weeks on memory and caches
1 1/2 weeks on Memory and I/O
2 weeks on special topics: low power, network as the
backplane, edge processors
• 2 weeks exams, presentations
Lec 1.23
Course Administration
 Instructor:Fu-Chiung Cheng ([email protected])
A5-707
Office Hours(Tentative):
Wens 11:00-12:00
 TAs:
TBA
 Materials:
http://www.cse.ttu.edu.tw/~cheng/courses/comporg
.htm
 Text: Patterson and Hennessy, Computer
Organization and Design: The Hardware/Software
Interface, 2nd Ed., 1998.
Hennessy and Patterson, Computer Architecture, A
Quant-itative Approach, 3rd Ed., 2003.
Lec 1.24
(recommended as an advanced reference)
Grading
 4 Tests
40%
 1 Midterm exam
25% (chap 1~4)
 1 Final exam
30% (chap 1-8)
 Participation in class
5%
Lec 1.25
Instructors’ Goals
 Show you how to understand modern computer
architecture in its rapidly changing form
 Show you how to design by leading you through the
process on challenging design problems
 Learn how to test things
 NOT to talk at you
 So ...
• ask questions
• come to office hours
• find me in the lab
• ...
Lec 1.26
Levels of Representation (61C Review)
temp = v[k];
High Level Language
Program
v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $15,
lw $16,
sw
sw
Assembly Language
Program
Assembler
Machine Language
Program
0000
1010
1100
0101
1001
1111
0110
1000
1100
0101
1010
0000
0($2)
4($2)
$16, 0($2)
$15, 4($2)
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Machine Interpretation
Control Signal
Specification
°
°
ALUOP[0:3] <= InstReg[9:11] & MASK
Lec 1.27
Execution Cycle
Instruction
Obtain instruction from program storage
Fetch
Instruction
Determine required actions and instruction size
Decode
Operand
Locate and obtain operand data
Fetch
Execute
Result
Store
Next
Instruction
Compute result value or status
Deposit results in storage for later use
Determine successor instruction
Lec 1.28
It’s All About Communication
Pentium III Chipset
Proc
Caches
Busses
Memory
adapters
Controllers
I/O Devices:
Disks
Displays
Keyboards
Networks
 All have interfaces & organizations
 Um…. It’s the network stupid???!
Lec 1.29
Summary
 All computers consist of five components
• Processor: (1) datapath and (2) control
• (3) Memory
• (4) Input devices and (5) Output devices
 Not all “memory” are created equally
• Cache: fast (expensive) memory are placed closer to the
processor
• Main memory: less expensive memory--we can have more
 Interfaces are where the problems are - between
functional units and between the computer and the
outside world
 Need to design against constraints of performance,
power, area and cost
Lec 1.30