Transcript Liu_TWEPP09_LCPLL_poster

The Design of a Low-Power High-Speed Phase Locked Loop
Tiankuan Liu1, Datao Gong1, Suen Hou2, Zhihua Liang1, Chonghan Liu1, Da-Shung Su2, Ping-Kun Teng2, Annie C. Xiang1, Jingbo Ye1
1
Department of Physics, Southern Methodist University, Dallas TX 75275, U.S.A.
2 Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan
[email protected]
Introduction
Application Background: ATLAS Liquid Argon
Calorimeter Optical Link Upgrade
Present
Upgrade
Data rate per front-end board (FEB) (Gbps)
1.6
100
Power consumption per Gbps (mW)
1188
90
Silicon-on-Sapphire (SoS) CMOS technology
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Design Goals
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High speed, low power, high quality inductors, no latch-up
The radiation tolerance of a commercial 0.25 µm SoS
CMOS technology has been evaluated in the previous
study
Operation frequency: 4 ~ 5 GHz for data rate 8 ~ 10 Gbps
Random jitter < 1 ps (RMS)
Power consumption < 100 mW
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Design
PLL block diagram
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VCO
The PLL consists of a phase frequency detector (PFD), a
charge pump, a low pass filter, a voltage controlled oscillator
(VCO), and a divider (divide by 16). An LVDS receiver and a
CML driver are used as the input and output interface. The
divider consists of a CML divider (divide by 2), a CML to
CMOS converter, and a CMOS divider (divide by 8).
The LVDS receiver, the phase frequency detector (PFD), the
charge pump, the pass filter, the CMOS divider, and the CML
driver are shared with the 5 Gbps 16:1 serializer. For details
of these design blocks please see the poster “A 16:1
serializer for data transmission at 5 Gbps ” presented by Dr.
Datao Gong.
The bandwidth of the low pass filter and the current of charge
pump are programmable to suit different applications. The
phase margin of the PLL is larger than 46°.
VCO Type
LC-based VCO
Ring-oscillator
based VCO
Power Consumption
Low
High
Frequency
High
Low
Phase noise/jitter performance
Good
Bad
Radiation sensitivity
Small
Large
Tuning range
Narrow
Wide
Chip area
Large
Small
A NMOS or PMOS transistor with its source and drain tied together
serves a varactor with monotonic C-V curve and large tuning range
(Cmax/Cmin > 2).
Cross-coupled transistors
provides negative
resistance, compensating
the energy loss in the LC
tank
Decoupling capacitors
are used to improve the
noise performance
PLL Layout
The tuning range is 3.79 – 5.01 GHz at the typical corner
and room temperature and varies less than 8% in all
corners and temperature range.
Start-up circuit
Reference current
source
On-chip spiral inductors
with a peak frequency of
5.1 GHz. The Q factor is
simulated to be 21.2 at 5
GHz.
CML Divider
1.4 mm x
1.7 mm
The CML divider can work
up to 5.1 GHz at all corners
and from -40 °C to 85 °C.
Performances
Acquisition Time
Deterministic Jitter
Random Jitter
The phase noise of the
VCO in the worst case
The PLL
tracks the
input
frequency
after 9 µs.
The jitter after 9 µs is
less than 2 ps (peakpeak).
Conclusion
Simulated results of the PLL
Acknowledgments
Status and Plan
Tuning range (GHz)
3.8 – 5.1
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Power consumption of core PLL (mW)
Area (mm2)
104
1.4 x 1.7
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Random Jitter from VCO (RMS, ps)
<1
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Deterministic jitter (peak-peak, ps)
Acquisition time (μs)
2
9
The random jitter due to
the VCO’s phase noise,
the dominant noise
source, is less than 1 ps
(RMS) from 10 kHz to
100 MHz.
Fabrication: submitted on August 3, 2009; Chip
delivery: November 17, 2009
Test: in lab test: December 15, 2009; Radiation
test: February 15, 2010
Plan: apply this LC-based PLL and design a
multi-channel 16:1 serializer with each channel
working around 10 Gbps in 2011
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Grant: US-ATLAS R&D program for the upgrade of the LHC and the US Department of
Energy grant DE-FG02-04ER41299.
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Peter Clarke, Jay Clementson, Yi Kang, Francis M. Rotella, John Sung, and Gary Wu
from Peregrine Semiconductor Corporation for technical assistance.
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Justin Ross at Southern Methodist University for setting up and maintaining the software
environment.
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Jasoslav Ban, Mauro Citterio, Christine Hu, Sachin Junnarkar, Valentino Liberali, Paulo
Rodrigues Simoes Moreira, Mitch Newcomer, Quan Sun, Fukun Tang, and Carla Vacchi
for technical assistance and reviewing of this design.