Transcript Testing in the Fourth Dimension

Electronic Testing for
SOC Designers
Vishwani D. Agrawal
Agere Systems, Murray Hill, NJ 07974 USA
[email protected]
Michael L. Bushnell
ECE Dept., Rutgers University
Piscataway, NJ 08854 USA
[email protected]
7th ASPDAC and 15th International Conference on
VLSI Design
Bangalore, India, January 8, 2002
January 8, 2002 (T5)
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Course Outline



Part I:
 Basic concepts and definitions
 Test process and ATE
 Test economics and product quality
 Fault modeling
Part II:
 Logic and fault simulation
 Combinational circuit ATPG
 Sequential circuit ATPG
 Memory test
 Analog test
 Delay test and IDDQ test
Part III:
 Scan design
 BIST
 Boundary scan and analog test bus
 System test and core-based design
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Part I
INTRODUCTION TO
TESTING
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VLSI Realization Process
Customer’s need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabrication
Manufacturing test
Chips to customer
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Definitions

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Design synthesis: Given an I/O function, develop
a procedure to manufacture a device using
known materials and processes.
Verification: Predictive analysis to ensure that
the synthesized design, when manufactured, will
perform the given I/O function.
Test: A manufacturing step that ensures that the
physical device, manufactured from the
synthesized design, has no manufacturing
defect.
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Realities of Tests


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Based on analyzable fault models, which
may not map onto real defects.
Incomplete coverage of modeled faults due
to high complexity.
Some good chips are rejected. The
fraction (or percentage) of such chips is
called the yield loss.
Some bad chips pass tests. The fraction
(or percentage) of bad chips among all
passing chips is called the defect level.
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Costs of Testing

Design for testability (DFT)
 Chip area overhead and yield reduction
 Performance overhead


Software processes of test
 Test generation and fault simulation
 Test programming and debugging
Manufacturing test
 Automatic test equipment (ATE) capital cost
 Test center operational cost
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Present and Future*
1997 -2001 2003 - 2006
Feature size (micron) 0.25 - 0.15 0.13 - 0.10
Transistors/sq. cm
4 - 10M
18 - 39M
Pin count
100 - 900 160 - 1475
Clock rate (MHz)
Power (Watts)
200 - 730
1.2 - 61
530 - 1100
2 - 96
* SIA Roadmap, IEEE Spectrum, July 1999
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Cost of Manufacturing
Testing in 2000AD



0.5-1.0GHz, analog instruments,1,024
digital pins: ATE purchase price
 = $1.2M + 1,024 x $3,000 = $4.272M
Running cost (five-year linear depreciation)
 = Depreciation + Maintenance + Operation
 = $0.854M + $0.085M + $0.5M
 = $1.439M/year
Test cost (24 hour ATE operation)
 = $1.439M/(365 x 24 x 3,600)
 = 4.5 cents/second
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VLSI Testing Process
and Equipment
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Testing Principle
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Automatic Test
Equipment Components

Consists of:
 Powerful computer
 Powerful 32-bit Digital Signal Processor
(DSP) for analog testing
 Test Program (written in high-level
language) running on the computer
 Probe Head (actually touches the bare
or packaged chip to perform fault
detection experiments)
 Probe Card or Membrane Probe
(contains electronics to measure signals
on chip pin or pad)
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Characterization Test


Worst-case test
 Choose test that passes/fails chips
 Select statistically significant sample of
chips
 Repeat test for every combination of 2+
environmental variables
 Plot results in Shmoo plot
 Diagnose and correct design errors
Continue throughout production life of chips
to improve design and process to increase
yield
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Shmoo Plot
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Manufacturing Test
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Determines whether manufactured chip
meets specs
Must cover high % of modeled faults
Must minimize test time (to control cost)
No fault diagnosis
Tests every device on chip
Test at speed of application or speed
guaranteed by supplier
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Burn-in or Stress Test


Process:
 Subject chips to high temperature & overvoltage supply, while running production
tests
Catches:
 Infant mortality cases – these are
damaged chips that will fail in the first 2
days of operation – causes bad devices to
actually fail before chips are shipped to
customers
 Freak failures – devices having same
failure mechanisms as reliable devices
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Types of Manufacturing
Tests


Wafer sort or probe test – done before
wafer is scribed and cut into chips
 Includes test site characterization –
specific test devices are checked with
specific patterns to measure:
 Gate threshold
 Polysilicon field threshold
 Poly sheet resistance, etc.
Packaged device tests
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Sub-types of Tests


Parametric – measures electrical
properties of pin electronics – delay,
voltages, currents, etc. – fast and cheap
Functional – used to cover very high % of
modeled faults – test every transistor and
wire in digital circuits – long and expensive
– main topic of tutorial
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Two Different Meanings
of Functional Test

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ATE and Manufacturing World – any vectors
applied to cover high % of faults during
manufacturing test
Automatic Test-Pattern Generation World –
testing with verification vectors, which
determine whether hardware matches its
specification – typically have low fault
coverage (< 70 %)
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Test Specifications & Plan


Test Specifications:
 Functional Characteristics
 Type of Device Under Test (DUT)
 Physical Constraints – Package, pin
numbers, etc.
 Environmental Characteristics – supply,
temperature, humidity, etc.
 Reliability – acceptance quality level
(defects/million), failure rate, etc.
Test plan generated from specifications
 Type of test equipment to use
 Types of tests
 Fault coverage requirement
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ADVANTEST Model
T6682 ATE
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LTX FUSION HF ATE
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Summary

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Parametric tests – determine whether pin electronics
system meets digital logic voltage, current, and delay
time specs
Functional tests – determine whether internal
logic/analog sub-systems behave correctly
ATE Cost Problems
 Pin inductance (expensive probing)
 Multi-GHz frequencies
 High pin count (1024)
ATE Cost Reduction
 Multi-Site Testing
 DFT methods like Built-In Self-Test
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Test Economics and
Product Quality
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Economics of Design for
Testability (DFT)


Consider life-cycle cost; DFT on chip may
impact the costs at board and system
levels.
Weigh costs against benefits


Cost examples: reduced yield due to area
overhead, yield loss due to non-functional
tests
Benefit examples: Reduced ATE cost due to
self-test, inexpensive alternatives to burn-in
test
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Benefits and Costs of DFT
Level
Design
and test
Fabrication
Chips
+/-
+
-
Boards
+/-
+
-
System
+/-
+
-
Manuf. Maintenance
Test
test
Diagnosis
Service
and repair interruption
-
-
-
+ Cost increase
- Cost saving
+/- Cost increase may balance cost reduction
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VLSI Chip Yield

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A manufacturing defect is a finite chip area
with electrically malfunctioning circuitry
caused by errors in the fabrication process.
A chip with no manufacturing defect is called
a good chip.
Fraction (or percentage) of good chips
produced in a manufacturing process is called
the yield. Yield is denoted by symbol Y.
Cost of a chip:
Cost of fabricating and testing a wafer
-------------------------------------------------------------------Yield x Number of chip sites on the wafer
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Defect Level or Reject Ratio
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Defect level (DL) is the ratio of faulty
chips among the chips that pass tests.
DL is measured as parts per million (ppm).
DL is a measure of the effectiveness of
tests.
DL is a quantitative measure of the
manufactured product quality. For
commercial VLSI chips a DL greater than
500 ppm is considered unacceptable.
January 8, 2002 (T5)
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Modified Yield Equation


Three parameters:
 Fault density, f = average number of
stuck-at faults per unit chip area
 Fault clustering parameter, b
 Stuck-at fault coverage, T
The modified yield equation:
Y (T ) = (1 + TAf / b) - b
Assuming that tests with 100% fault coverage
(T =1.0) remove all faulty chips,
Y = Y (1) = (1 + Af / b) - b
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Defect Level
Y (T ) - Y (1)
DL (T ) = -------------------Y (T )
b
( b + TAf )
= 1 - -------------------b
( b + Af )
Where T is the fault coverage of tests,
Af is the average number of faults on the
chip of area A, b is the fault clustering
parameter. Af and b are determined by
test data analysis.
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Example: SEMATECH Chip

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Bus interface controller ASIC fabricated
and tested at IBM, Burlington, Vermont
116,000 equivalent (2-input NAND) gates
304-pin package, 249 I/O
Clock: 40MHz, some parts 50MHz
0.45m CMOS, 3.3V, 9.4mm x 8.8mm area
Full scan, 99.79% fault coverage
Advantest 3381 ATE, 18,466 chips tested
at 2.5MHz test clock
Data obtained courtesy of Phil Nigh (IBM)
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Stuck-at fault coverage
Test Coverage from
Fault Simulator
Vector number
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Measured chip fallout
Measured Chip Fallout
Vector number
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Chip fallout and computed 1-Y (T )
Model Fitting
Chip fallout vs. fault coverage
Y (1) = 0.7623
Measured chip fallout
Y (T ) for Af = 2.1 and b = 0.083
Stuck-at fault coverage, T
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Computed DL
Defect level in ppm
237,700 ppm (Y = 76.23%)
Stuck-at fault coverage (%)
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Summary
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
VLSI yield depends on two process parameters,
defect density (d ) and clustering parameter (a)
Yield drops as chip area increases; low yield
means high cost
Fault coverage measures the test quality
Defect level (DL) or reject ratio is a measure of
chip quality
DL can be determined by an analysis of test
data
For high quality: DL < 500 ppm, fault coverage
~ 99%
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Fault Modeling
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Why Model Faults?

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I/O function tests inadequate for
manufacturing (functionality versus
component and interconnect testing)
Real defects (often mechanical) too
numerous and often not analyzable
A fault model identifies targets for testing
A fault model makes analysis possible
Effectiveness measurable by experiments
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Some Real Defects in Chips




Processing defects
 Missing contact windows
 Parasitic transistors
 Oxide breakdown
 . . .
Material defects
 Bulk defects (cracks, crystal imperfections)
 Surface impurities (ion migration)
 . . .
Time-dependent failures
 Dielectric breakdown
 Electromigration
 . . .
Packaging failures
 Contact degradation
 Seal leaks
 . . .
Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation Semiconductor Devices and Circuits, Wiley, 1981.
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Observed PCB Defects
Occurrence frequency (%)
Defect classes
Shorts
Opens
Missing components
Wrong components
Reversed components
Bent leads
Analog specifications
Digital logic
Performance (timing)
51
1
6
13
6
8
5
5
5
Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985.
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Common Fault Models
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Single stuck-at faults
Transistor open and short faults
Memory faults
PLA faults (stuck-at, cross-point, bridging)
Functional faults (processors)
Delay faults (transition, path)
Analog faults
For more examples, see Section 4.4 (p. 6070) of the book.
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Single Stuck-at Fault

Three properties define a single stuck-at fault

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
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Only one line is faulty
The faulty line is permanently set to 0 or 1
The fault can be at an input or output of a gate
Example: XOR circuit has 12 fault sites ( ) and
24 single stuck-at faults
c
1
0
a
d
b
e
f
Faulty circuit value
Good circuit value
j
s-a-0
g
1
0(1)
1(0)
h
i
z
1
k
Test vector for h s-a-0 fault
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Fault Equivalence

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

Number of fault sites in a Boolean gate circuit
= #PI + #gates + #(fanout branches).
Fault equivalence: Two faults f1 and f2 are
equivalent if all tests that detect f1 also
detect f2.
If faults f1 and f2 are equivalent then the
corresponding faulty functions are identical.
Fault collapsing: All single faults of a logic
circuits can be divided into disjoint
equivalence subsets, where all faults in a
subset are mutually equivalent. A collapsed
fault set contains one fault from each
equivalence subset.
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Equivalence Rules
sa0 sa1
sa0
sa0
sa1
sa1
sa0 sa1
AND
sa0 sa1
sa0 sa1
OR
WIRE
sa0 sa1
sa0 sa1
sa0
sa1
sa0 sa1
NOT
sa1
sa0
sa0 sa1
NAND
sa0 sa1
sa0 sa1
NOR
sa0 sa1
sa0 sa1
sa0
sa1
FANOUT
January 8, 2002 (T5)
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sa0
sa1
sa0
sa1
44
Equivalence Example
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
Faults in red
removed by
equivalence
collapsing
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
sa0 sa1
20
Collapse ratio = ----- = 0.625
32
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Fault Dominance

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If all tests of some fault F1 detect another fault
F2, then F2 is said to dominate F1.
Dominance fault collapsing: If fault F2
dominates F1, then F2 is removed from the
fault list.
When dominance fault collapsing is used, it is
sufficient to consider only the input faults of
Boolean gates. See the next example.
In a tree circuit (without fanouts) PI faults form
a dominance collaped fault set.
If two faults dominate each other then they are
equivalent.
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Dominance Example
All tests of F2
F1
s-a-1
F2
s-a-1
110
101
s-a-1
001
000
100
010
011
Only test of F1
s-a-1
s-a-1
s-a-0
A dominance collapsed fault set
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Checkpoints


Primary inputs and fanout branches of a
combinational circuit are called checkpoints.
Checkpoint theorem: A test set that detects
all single (multiple) stuck-at faults on all
checkpoints of a combinational circuit, also
detects all single (multiple) stuck-at faults in
that circuit.
Total fault sites = 16
Checkpoints ( ) = 10
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Classes of Stuck-at Faults

Following classes of single stuck-at faults are
identified by fault simulators:

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


Potentially-detectable fault -- Test produces an
unknown (X) state at PO; detection is
probabilistic, usually with 50% probability.
Initialization fault -- Fault prevents initialization of
the faulty circuit; can be detected as a potentiallydetectable fault.
Hyperactive fault -- Fault induces much internal
signal activity without reaching PO.
Redundant fault -- No test exists for the fault.
Untestable fault -- Test generator is unable to find
a test.
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Summary





Fault models are analyzable approximations of
defects and are essential for a test
methodology.
For digital logic single stuck-at fault model
offers best advantage of tools and experience.
Many other faults (bridging, stuck-open and
multiple stuck-at) are largely covered by
stuck-at fault tests.
Stuck-short and delay faults and technologydependent faults require special tests.
Memory and analog circuits need other
specialized fault models and tests.
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Part II
TEST METHODS
Logic Simulation
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Simulation Defined



Definition: Simulation refers to modeling of a
design, its function and performance.
A software simulator is a computer program;
an emulator is a hardware simulator.
Simulation is used for design verification:




Validate assumptions
Verify logic
Verify performance (timing)
Types of simulation:




Logic or switch level
Timing
Circuit
Fault
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Simulation for Verification
Specification
Synthesis
Response Design Design
analysis changes (netlist)
Computed
responses
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True-value
simulation
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Input stimuli
53
Modeling for Simulation

Modules, blocks or components described by




Interconnects represent



Input/output (I/O) function
Delays associated with I/O signals
Examples: binary adder, Boolean gates, FET,
resistors and capacitors
ideal signal carriers, or
ideal electrical conductors
Netlist: a format (or language) that describes
a design as an interconnection of modules.
Netlist may use hierarchy.
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Example: A Full-Adder
c
a
e
d
b
A
B
C
HA
HA1
January 8, 2002 (T5)
D
E
HA2
F
f
Carry
Sum
HA;
inputs: a, b;
outputs: c, f;
AND: A1, (a, b), (c);
AND: A2, (d, e), (f);
OR: O1, (a, b), (d);
NOT: N1, (c), (e);
FA;
inputs: A, B, C;
outputs: Carry, Sum;
HA: HA1, (A, B), (D, E);
HA: HA2, (E, C), (F, Sum);
OR: O2, (D, F), (Carry);
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Logic Model of MOS Circuit
pMOS FETs
a
b
Ca
Cb
VDD
Cc
c
Da
b
Db
nMOS FETs
Ca , Cb and Cc are
parasitic capacitances
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a
c
Dc
Da and Db are
interconnect or
propagation delays
Dc is inertial delay
of gate
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Options for Inertial Delay
Inputs
(simulation of a NAND gate)
Transient
region
a
b
Logic simulation
c (CMOS)
c (zero delay)
c (unit delay)
X
c (multiple delay)
Unknown (X)
c (minmax delay)
0
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rise=5, fall=5
min =2, max =5
Time units
57
Signal States

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

Two-states (0, 1) can be used for purely
combinational logic with zero-delay.
Three-states (0, 1, X) are essential for
timing hazards and for sequential logic
initialization.
Four-states (0, 1, X, Z) are essential for MOS
devices. See example below.
Analog signals are used for exact timing of
digital logic and for analog circuits.
Z
(hold previous value)
0
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0
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Modeling Levels
Timing
Application
Clock
boundary
Architectural
and functional
verification
0, 1, X
and Z
Zero-delay
unit-delay,
multipledelay
Logic
verification
and test
0, 1
and X
Zero-delay
Logic
verification
Fine-grain
timing
Timing
verification
Continuous
time
Digital timing
and analog
circuit
verification
Modeling
level
Circuit
description
Function,
behavior, RTL
Programming
language-like HDL
Logic
Connectivity of
Boolean gates,
flip-flops and
transistors
Switch
Transistor size
and connectivity,
node capacitances
Timing
Transistor technology Analog
voltage
data, connectivity,
node capacitances
Circuit
Tech. Data, active/
passive component
connectivity
January 8, 2002 (T5)
Signal
values
0, 1
Analog
voltage,
current
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True-Value Simulation
Algorithms

Compiled-code simulation





Applicable to zero-delay combinational logic
Also used for cycle-accurate synchronous sequential
circuits for logic verification
Efficient for highly active circuits, but inefficient for
low-activity circuits
High-level (e.g., C language) models can be used
Event-driven simulation




Only gates or modules with input events are
evaluated (event means a signal change)
Delays can be accurately simulated for timing
verification
Efficient for low-activity circuits
Can be extended for fault simulation
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Compiled-Code Algorithm



Step 1: Levelize combinational logic and
encode in a compilable programming language
Step 2: Initialize internal state variables (flipflops)
Step 3: For each input vector
 Set primary input variables
 Repeat (until steady-state or max. iterations)

Execute compiled code
 Report or save computed variables
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Event-Driven Algorithm
(Example)
2
0
e =1
t=0
2
2
d=0
4
b =1
f =0
g
0
4
8
2
c=0
d, e
d = 1, e = 0
f, g
Time, t
3
4
Electronic Testing: Agrawal & Bushnell
g=0
5
6
f=1
g
7
8
January 8, 2002 (T5)
Activity
list
1
g =1
Time stack
a =1
c =1
Scheduled
events
g=1
62
Efficiency of Eventdriven Simulator


Simulates events (value changes) only
Speed up over compiled-code can be ten
times or more; in large logic circuits about
0.1 to 10% gates become active for an input
change
Steady 0
0 to 1 event
January 8, 2002 (T5)
Steady 0
(no event)
Large logic
block without
activity
Electronic Testing: Agrawal & Bushnell
63
Summary





Logic or true-value simulators are essential
tools for design verification.
Verification vectors and expected responses
are generated (often manually) from
specifications.
A logic simulator can be implemented using
either compiled-code or event-driven method.
Per vector complexity of a logic simulator is
approximately linear in circuit size.
Modeling level determines the evaluation
procedures used in the simulator.
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
64
Fault Simulation
January 8, 2002 (T5)
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65
Problem and Motivation

Fault simulation Problem: Given



A circuit
A sequence of test vectors
A fault model
 Determine



Fault coverage - fraction (or percentage) of
modeled faults detected by test vectors
Set of undetected faults
Motivation


Determine test quality and in turn product quality
Find undetected fault targets to improve tests
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
66
Fault simulator in a VLSI
Design Process
Verified design
netlist
Verification
input stimuli
Fault simulator
Test vectors
Modeled
Remove
fault list tested faults
Fault
coverage
?
Low
Test
Delete
compactor vectors
Test
generator
Add vectors
Adequate
Stop
January 8, 2002 (T5)
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67
Fault Simulation Scenario

Circuit model: mixed-level



Signal states: logic



Mostly logic with some switch-level for highimpedance (Z) and bidirectional signals
High-level models (memory, etc.) with pin faults
Two (0, 1) or three (0, 1, X) states for purely
Boolean logic circuits
Four states (0, 1, X, Z) for sequential MOS circuits
Timing:


Zero-delay for combinational and synchronous
circuits
Mostly unit-delay for circuits with feedback
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
68
Fault Simulation Scenario
(continued)

Faults:





Mostly single stuck-at faults
Sometimes stuck-open, transition, and path-delay
faults; analog circuit fault simulators are not yet in
common use
Equivalence fault collapsing of single stuck-at
faults
Fault-dropping -- a fault once detected is dropped
from consideration as more vectors are simulated;
fault-dropping may be suppressed for diagnosis
Fault sampling -- a random sample of faults is
simulated when the circuit is large
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
69
Fault Simulation
Algorithms





January 8, 2002 (T5)
Serial
Parallel
Deductive
Concurrent
Differential
Electronic Testing: Agrawal & Bushnell
70
Serial Algorithm

Algorithm: Simulate fault-free circuit and save
responses. Repeat following steps for each
fault in the fault list:




Modify netlist by injecting one fault
Simulate modified netlist, vector by vector,
comparing responses with saved responses
If response differs, report fault detection and
suspend simulation of remaining vectors
Advantages:


Easy to implement; needs only a true-value
simulator, less memory
Most faults, including analog faults, can be
simulated
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
71
Serial Algorithm (Cont.)


Disadvantage: Much repeated computation;
CPU time prohibitive for VLSI circuits
Alternative: Simulate many faults together
Test vectors
Fault-free circuit
Comparator
f1 detected?
Comparator
f2 detected?
Comparator
fn detected?
Circuit with fault f1
Circuit with fault f2
Circuit with fault fn
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
72
Parallel Fault Simulation






Compiled-code method; best with twostates (0,1)
Exploits inherent bit-parallelism of logic
operations on computer words
Storage: one word per line for two-state
simulation
Multi-pass simulation: Each pass simulates
w-1 new faults, where w is the machine
word length
Speed up over serial method ~ w-1
Not suitable for circuits with timing-critical
and non-Boolean logic
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
73
Parallel Fault Sim. Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
1
a
b
1
1
1
1
1
1
1
c
0
1
1
e
1
s-a-0
0
d
January 8, 2002 (T5)
0
c s-a-0 detected
0
f
0
s-a-1
0
0
Electronic Testing: Agrawal & Bushnell
0
1
g
1
74
Deductive Fault Simulation





One-pass simulation
Each line k contains a list Lk of faults
detectable on k
Following true-value simulation of each
vector, fault lists of all gate output lines
are updated using set-theoretic rules,
signal values, and gate input fault lists
PO fault lists provide detection data
Limitations:


Set-theoretic rules difficult to derive for nonBoolean gates
Gate delays are difficult to use
January 8, 2002 (T5)
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75
Concurrent Fault Simulation





Event-driven simulation of fault-free circuit and
only those parts of the faulty circuit that differ
in signal states from the fault-free circuit.
A list per gate containing copies of the gate
from all faulty circuits in which this gate differs.
List element contains fault ID, gate input and
output values and internal states, if any.
All events of fault-free and all faulty circuits are
implicitly simulated.
Faults can be simulated in any modeling style or
detail supported in true-value simulation (offers
most flexibility.)
Faster than other methods, but uses most
memory.
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
76
Conc. Fault Sim. Example
0
0
1
a
b
1
1
1
c
d
1
1
1 0
c0
b0
a0
1
1
0
0
0
e0
0
0 1
January 8, 2002 (T5)
0
1
1
e
1
0
0
f
d0
0
0 1
f1
1 1
1
1
0
b0
1
a0
g
0
0
1
1
0
0
g
0
Electronic Testing: Agrawal & Bushnell
b0
0
1
0
1
1
1
f1
c0
0
0
0
1
1
e0
0
1
d0
77
Fault Sampling




A randomly selected subset (sample) of
faults is simulated.
Measured coverage in the sample is used
to estimate fault coverage in the entire
circuit.
Advantage: Saving in computing resources
(CPU time and memory.)
Disadvantage: Limited data on undetected
faults.
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
78
Random Sampling Model
Detected
fault
All faults with
a fixed but
unknown
coverage
Random
picking
Np = total number of faults
Ns = sample size
Ns << Np
(population size)
C = fault coverage (unknown)
January 8, 2002 (T5)
Undetected
fault
c = sample coverage
Electronic Testing: Agrawal & Bushnell
(a random variable)
79
Probability Density of
Sample Coverage, c
(x--C )2
-- ------------
1
p (x ) = Prob(x < c < x +dx ) = -------------- e
s (2 p)
2s
2
1/2
p (x )
C (1 - C)
2
Variance, s = -----------Ns
s
Sampling
error
s
Mean = C
C -3s
C
x
C +3s 1.0
x
Sample coverage
January 8, 2002 (T5)
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80
Sampling Error Bounds
|x-C|=3
C (1 - C )
1/2
[ -------------]
N
s
Solving the quadratic equation for C, we get the
3-sigma (99.7% confidence) estimate:
4.5
C 3s = x  ------- [1 + 0.44 Ns x (1 - x )]1/2
Ns
Where Ns is sample size and x is the measured fault
coverage in the sample.
Example: A circuit with 39,096 faults has an actual
fault coverage of 87.1%. The measured coverage in
a random sample of 1,000 faults is 88.7%. The above
formula gives an estimate of 88.7% 3%. CPU time for
sample simulation was about 10% of that for all faults.

January 8, 2002 (T5)
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81
Summary




Fault simulator is an essential tool for test development.
Concurrent fault simulation algorithm offers the best
choice.
For restricted class of circuits (combinational and
synchronous sequential with only Boolean primitives),
differential algorithm can provide better speed and
memory efficiency (Section 5.5.6.)
For large circuits, the accuracy of random fault sampling
only depends on the sample size (1,000 to 2,000 faults)
and not on the circuit size. The method has significant
advantages in reducing CPU time and memory needs of
the simulator.
January 8, 2002 (T5)
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82
Combinational
Automatic Test-pattern
Generation
January 8, 2002 (T5)
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83
Functional vs. Structural
ATPG
January 8, 2002 (T5)
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84
Carry Circuit
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
85
Functional vs. Structural
(Continued)



Functional ATPG – generate complete set of tests for
circuit input-output combinations
 129 inputs, 65 outputs:
 2129 = 680,564,733,841,876,926,926,749,
214,863,536,422,912 patterns
 Using 1 GHz ATE, would take 2.15 x 1022 years
Structural test:
 No redundant adder hardware, 64 bit slices
 Each with 27 faults (using fault equivalence)
 At most 64 x 27 = 1728 faults (tests)
 Takes 0.000001728 s on 1 GHz ATE
Designer gives small set of functional tests – augment
with structural tests to boost coverage to 98+ %
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
86
Definition of Automatic
Test-Pattern Generator

Operations on digital hardware:
 Inject fault into circuit modeled in computer
 Use various ways to activate and propagate
fault effect through hardware to circuit output
 Output flips from expected to faulty signal
January 8, 2002 (T5)
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87
Circuit and Binary
Decision Tree
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
88
Algorithm Completeness



Definition: Algorithm is complete if it
ultimately can search entire binary
decision tree, as needed, to generate a
test
Untestable fault – no test for it even after
entire tree searched
Combinational circuits only – untestable
faults are redundant, showing the
presence of unnecessary hardware
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
89
Algebras: Roth’s 5-Valued
and Muth’s 9-Valued
Failing
Good
Symbol Meaning Machine Machine Remarks
D
D
0
1
X
G0
G1
F0
F1
January 8, 2002 (T5)
1/0
0/1
0/0
1/1
X/X
0/X
1/X
X/0
X/1
1
0
0
1
X
0
1
X
X
0
1
0
1
X
X
X
0
1
Electronic Testing: Agrawal & Bushnell
Roth’s
Algebra
Muth’s
Additions
90
Random-Pattern Generation


Flow chart for
method
Use to get
tests for 6080% of faults,
then switch to
D-algorithm or
other ATPG
for rest
January 8, 2002 (T5)
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91
Path Sensitization Method
Circuit Example
1 Fault Sensitization
2 Fault Propagation
3 Line Justification
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
92
Path Sensitization Method
Circuit Example
 Try path f – h – k – L blocked at j, since
there is no way to justify the 1 on i
1
1
D
D
D
D
1
0
D
1
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
93
Path Sensitization Method
Circuit Example
 Try simultaneous paths f – h – k – L and
g – i – j – k – L blocked at k because
D-frontier (chain of D or D) disappears
1
1
D
D
1
D
January 8, 2002 (T5)
D
D
Electronic Testing: Agrawal & Bushnell
94
Path Sensitization Method
Circuit Example
 Final try: path g – i – j – k – L – test found!
0
1
0
D
D
D
D
D
1
1
January 8, 2002 (T5)
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95
History of Algorithm
Speedups
Algorithm
Est. speedup over D-ALG Year
(normalized to D-ALG time)
D-ALG
1
1966
PODEM
7
1981
FAN
23
1983
TOPS
292
1987
SOCRATES
1574 † ATPG System
1988
Waicukauski et al. 2189 † ATPG System
1990
EST
8765 † ATPG System
1991
TRAN
3005 † ATPG System
1993
Recursive learning 485
1995
Tafertshofer et al. 25057
1997
January 8, 2002 (T5)
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96
Analog Fault Modeling
Impractical for Logic ATPG



Huge # of different possible analog faults
in digital circuit
Exponential complexity of ATPG algorithm
– a 20 flip-flop circuit can take days of
computing
 Cannot afford to go to a lower-level
model
Most test-pattern generators for digital
circuits cannot even model at the
transistor switch level (see textbook for 5
examples of switch-level ATPG)
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
97
Fault Cone and D-frontier


Fault Cone -- Set of hardware affected by fault
D-frontier – Set of gates closest to POs with fault
effect(s) at input(s)
D-frontier
Fault Cone
January 8, 2002 (T5)
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98
Forward Implication


January 8, 2002 (T5)
Results in logic gate inputs
that are significantly
labeled so that output is
uniquely determined
AND gate forward
implication table:
Electronic Testing: Agrawal & Bushnell
99
Backward Implication

Unique determination of all gate inputs when
the gate output and some of the inputs are given
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
100
Implication Stack after
Backtrack
Unexplored
Present Assignment
Searched and Infeasible
0
0
January 8, 2002 (T5)
F
1
E
0
B
B
0
1
0
1
F
Electronic Testing: Agrawal & Bushnell
1
1
0
F
1
101
Branch-and-Bound Search



Efficiently searches binary search tree
Branching – At each tree level, selects
which input variable to set to what value
Bounding – Avoids exploring large tree
portions by artificially restricting search
decision choices
 Complete exploration is impractical
 Uses heuristics
January 8, 2002 (T5)
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102
Sequential Automatic
Test-pattern Generation
January 8, 2002 (T5)
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103
Sequential Circuits


A sequential circuit has memory in
addition to combinational logic.
Test for a fault in a sequential circuit is a
sequence of vectors, which




Initializes the circuit to a known state
Activates the fault, and
Propagates the fault effect to a primary
output
Methods of sequential circuit ATPG


Time-frame expansion methods
Simulation-based methods
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
104
Concept of Time-Frames

If the test sequence for a single stuck-at
fault contains n vectors,



Replicate combinational logic block n times
Place fault in each block
Generate a test for the multiple stuck-at fault
using combinational ATPG with 9-valued logic
Fault
Unknown
or given
Init. state
Comb.
block
January 8, 2002 (T5)
Vector -n+1
Timeframe
-n+1
PO -n+1
State
variables
Vector -1
Vector 0
Timeframe
-1
Timeframe
0
PO -1
PO 0
Electronic Testing: Agrawal & Bushnell
Next
state
105
Example for Logic Systems
FF1
A
s-a-1
January 8, 2002 (T5)
B
FF2
Electronic Testing: Agrawal & Bushnell
106
Nine-Valued Logic (Muth)
0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A 0
A X
s-a-1
s-a-1
0/1
FF1
FF2
X/1
X
0/X
0/X
X
0/1
X/1
Time-frame -1
January 8, 2002 (T5)
B X
Time-frame 0
Electronic Testing: Agrawal & Bushnell
B
FF1
FF2
0/1
107
Implementation of ATPG






Select a PO for fault detection based on drivability
analysis.
Place a logic value, 1/0 or 0/1, depending on fault
type and number of inversions.
Justify the output value from PIs, considering all
necessary paths and adding backward time-frames.
If justification is impossible, then use drivability to
select another PO and repeat justification.
If the procedure fails for all reachable POs, then the
fault is untestable.
If 1/0 or 0/1 cannot be justified at any PO, but 1/X or
0/X can be justified, the the fault is potentially
detectable.
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
108
Complexity of ATPG

Synchronous circuit -- All flip-flops controlled by clocks;
PI and PO synchronized with clock:
 Cycle-free circuit – No feedback among flip-flops:
Test generation for a fault needs no more than
dseq + 1 time-frames, where dseq is the
sequential depth.
 Cyclic circuit – Contains feedback among flipflops: May need 9Nff time-frames, where Nff is the
number of flip-flops.
Asynchronous circuit – Higher complexity!

Smax
TimeFrame
max-1
TimeFrame
max-2
S3
Time- S2 Time- S1 TimeFrame
Frame
Frame
-2
-1
0
S0
max = Number of distinct vectors with 9-valued elements = 9Nff
January 8, 2002 (T5)
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109
Cycle-Free Circuits




Characterized by absence of cycles among
flip-flops and a sequential depth, dseq.
dseq is the maximum number of flip-flops
on any path between PI and PO.
Both good and faulty circuits are
initializable.
Test sequence length for a fault is bounded
by dseq + 1.
January 8, 2002 (T5)
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110
Cycle-Free Example
Circuit
F2
2
F3
F1
Level = 1
3
F2
2
s - graph
F1
F3
Level = 1
3
dseq = 3
All faults are testable. See Example 8.6.
January 8, 2002 (T5)
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111
Cyclic Circuit Example
Modulo-3 counter
CNT
F2
F1
Z
s - graph
F1
January 8, 2002 (T5)
F2
Electronic Testing: Agrawal & Bushnell
112
Adding Initializing Hardware
Initializable modulo-3 counter
CNT
F2
F1
s-a-0
Z
s-a-1
CLR
s-a-1
s-a-1
Untestable fault
Potentially detectable fault
s - graph
F1
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
F2
113
Benchmark Circuits
Circuit
PI
PO
FF
Gates
Structure
Seq. depth
Total faults
Detected faults
Potentially detected faults
Untestable faults
Abandoned faults
Fault coverage (%)
Fault efficiency (%)
Max. sequence length
Total test vectors
Gentest CPU s (Sparc 2)
January 8, 2002 (T5)
s1196
14
14
18
529
Cycle-free
4
1242
1239
0
3
0
99.8
100.0
3
313
10
s1238
14
14
18
508
Cycle-free
4
1355
1283
0
72
0
94.7
100.0
3
308
15
Electronic Testing: Agrawal & Bushnell
s1488
8
19
6
653
Cyclic
-1486
1384
2
26
76
93.1
94.8
24
525
19941
s1494
8
19
6
647
Cyclic
-1506
1379
2
30
97
91.6
93.4
28
559
19183
114
Simulation-based ATPG

Difficulties with time-frame method:







Long initialization sequence
Impossible initialization with three-valued logic
(Section 5.3.4)
Circuit modeling limitations
Timing problems – tests can cause
races/hazards
High complexity
Inadequacy for asynchronous circuits
Advantages of simulation-based methods




Advanced fault simulation technology
Accurate simulation model exists for verification
Variety of tests – functional, heuristic, random
Used since early 1960s
January 8, 2002 (T5)
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115
Using Fault Simulator
Generate
new trial
vectors
No
Yes
Vector source:
Functional (test-bench),
Heuristic (walking 1, etc.),
Weighted random,
random
Trial vectors
Stopping
criteria (fault
Fault
simulator
coverage, CPU
time limit, etc.)
Restore
circuit
state
satisfied?
Stop
January 8, 2002 (T5)
Fault
list
No
New faults
detected?
Yes
Electronic Testing: Agrawal & Bushnell
Update
fault
list
Append
vectors
Test
vectors
116
Background







Seshu and Freeman, 1962, Asynchronous circuits,
parallel fault simulator, single-input changes vectors.
Breuer, 1971, Random sequences, sequential circuits
Agrawal and Agrawal, 1972, Random vectors followed
by D-algorithm, combinational circuits.
Shuler, et al., 1975, Concurrent fault simulator, random
vectors, sequential circuits.
Parker, 1976, Adaptive random vectors, combinational
circuits.
Agrawal, Cheng and Agrawal, 1989, Directed search
with cost-function, concurrent fault simulator,
sequential circuits.
Srinivas and Patnaik, 1993, Genetic algorithms; Saab,
et al., 1996; Corno, et al., 1996; Rudnick, et al., 1997;
Hsiao, et al., 1997.
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
117
Genetic Algorithms (GAs)

Theory of evolution by natural selection (Darwin, 1809-82.)





C. R. Darwin, On the Origin of Species by Means of Natural
Selection, London: John Murray, 1859.
J. H. Holland, Adaptation in Natural and Artificial Systems,
Ann Arbor: University of Michigan Press, 1975.
D. E. Goldberg, Genetic Algorithms in Search,
Optimization, and Machine Learning, Reading,
Massachusetts: Addison-Wesley, 1989.
P. Mazumder and E. M. Rudnick, Genetic Algorithms for
VLSI Design, Layout and Test Automation, Upper Saddle
River, New Jersey, Prentice Hall PTR, 1999.
Basic Idea: Population improves with each generation.



Population
Fitness criteria
Regeneration rules
January 8, 2002 (T5)
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118
Strategate Results
s1423
s5378
s35932
Total faults
1,515
4,603
39,094
Detected faults
1,414
3,639
35,100
Fault coverage
93.3%
79.1%
Test vectors
3,943
11,571
1.3 hrs.
37.8 hrs.
CPU time
HP J200 256MB
89.8%
257
10.2 hrs.
Ref.: M. S. Hsiao, E. M. Rudnick and J. H. Patel, “Dynamic State
Traversal for Sequential Circuit Test Generation,” ACM Trans.
on Design Automation of Electronic Systems (TODAES), vol. 5,
no. 3, July 2000.
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
119
Summary

Combinational ATPG algorithms are extended:




Cycle-free circuits:



Require at most dseq time-frames
Always initializable
Cyclic circuits:




Time-frame expansion unrolls time as combinational array
Nine-valued logic system
Justification via backward time
May need 9Nff time-frames
Circuit must be initializable
Partial scan can make circuit cycle-free (Chapter 14)
Asynchronous circuits:



High complexity
Low coverage and unreliable tests
Simulation-based methods are more useful (Section 8.3)
January 8, 2002 (T5)
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120
Memory Test
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
121
Memory Cells Per Chip
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
122
Test Time in Seconds
(Memory Size n Bits)
Size
Number of Test Algorithm Operations
n
n
n X log2n
1 Mb
4 Mb
16 Mb
64 Mb
256 Mb
1 Gb
2 Gb
0.06
0.25
1.01
4.03
16.11
64.43
128.9
1.26
5.54
24.16
104.7
451.0
1932.8
3994.4
January 8, 2002 (T5)
n3/2
n2
64.5
18.3 hr
515.4
293.2 hr
1.2 hr
4691.3 hr
9.2 hr
75060.0 hr
73.3 hr
1200959.9 hr
586.4 hr 19215358.4 hr
1658.6 hr 76861433.7 hr
Electronic Testing: Agrawal & Bushnell
123
March Test Notation

r -- Read a memory location

w -- Write a memory location

r0 -- Read a 0 from a memory location

r1 -- Read a 1 from a memory location

w0 -- Write a 0 to a memory location

w1 -- Write a 1 to a memory location

-- Write a 1 to a cell containing 0

-- Write a 0 to a cell containing 1
January 8, 2002 (T5)
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124
March Test Notation
(Continued)

-- Complement the cell contents

-- Increasing memory addressing

-- Decreasing memory addressing

-- Either increasing or decreasing
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
125
MATS+ March Test
M0: { March element (w0) }
for cell := 0 to n - 1 (or any other order) do
write 0 to A [cell];
M1: { March element
(r0, w1) }
for cell := 0 to n - 1 do
read A [cell]; { Expected value = 0}
write 1 to A [cell];
M2: {March element
(r1, w0) }
for cell := n – 1 down to 0 do
read A [cell]; { Expected value = 1 }
write 0 to A [cell];
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
126
Reduced Functional
Faults
SAF
TF
CF
NPSF
January 8, 2002 (T5)
Fault
Stuck-at fault
Transition fault
Coupling fault
Neighborhood Pattern Sensitive fault
Electronic Testing: Agrawal & Bushnell
127
Transition Faults

Cell fails to make 0

Condition: Each cell must undergo a transition
and a
1 or 1
0 transition
transition, and be read after such,
before undergoing any further transitions.

< / 0>, <
/ 1>
<
January 8, 2002 (T5)
/ 0> transition fault
Electronic Testing: Agrawal & Bushnell
128
Coupling Faults





Coupling Fault (CF): Transition in bit j causes
unwanted change in bit i
2-Coupling Fault: Involves 2 cells, special case of
k-Coupling Fault
 Must restrict k cells to make practical
Inversion and Idempotent CFs -- special cases of
2-Coupling Faults
Bridging and State Coupling Faults involve any #
of cells, caused by logic level
Dynamic Coupling Fault (CFdyn) -- Read or write
on j forces i to 0 or 1
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
129
Idempotent Coupling
Faults (CFid)


or transition in j sets cell i to 0 or 1
Condition: For all coupled faults, each should be
read after a series of possible CFids may have
happened, such that the sensitized CFids do not
mask each other.

Asymmetric: coupled cell only does

Symmetric: coupled cell does both due to fault

< ; 0>, < ; 1>, < ; 0>, < ; 1>
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
or
130
Address Decoder Faults



Address decoding error assumptions:
 Decoder does not become sequential
 Same behavior during both read & write
Multiple ADFs must be tested for
Decoders have CMOS stuck-open faults
January 8, 2002 (T5)
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131
Fault Modeling Example
SA1
gg
SA1+SCF
ABF
ABF
SA0
SCF
ABF
January 8, 2002 (T5)
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132
Fault Hierarchy
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
133
Fault Frequency


Obtained with Scanning Electron Microscope
CFin and TF faults rarely occurred
Cluster
0
1
2
3
4
5
7
-14
January 8, 2002 (T5)
# Devices
714
169
18
9
8
5
26
-2
Fault class
Stuck-at and Total failure
Stuck-open
Idempotent coupling
State coupling
?
?
Data retention
?
?
Electronic Testing: Agrawal & Bushnell
134
Functional RAM Testing
with March Tests


March Tests can detect AFs -- NPSF Tests
Cannot
Conditions for AF detection:
 Need
 Need

( r x, w x)
( r x, w x)
In the following March tests, addressing
orders can be interchanged
January 8, 2002 (T5)
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135
Irredundant March Test
Summary
Algorithm
MATS
MATS+
MATS++
MARCH X
MARCH C—
MARCH A
MARCH Y
MARCH B
January 8, 2002 (T5)
SAF
AF
TF CF CF CF SCF Linked
in id dyn
Faults
All Some
All
All
All
All
All
All
All All
All
All
All All All All
All
All
All All
All
All
All All
All
All
All All
All
Electronic Testing: Agrawal & Bushnell
All
Some
Some
Some
136
MATS+ Example
Cell (2, 1) SA1 Fault
MATS+:
{ M0: (w0); M1:
January 8, 2002 (T5)
(r0, w1); M2:
Electronic Testing: Agrawal & Bushnell
(r1, w0) }
137
Memory Testing
Summary



Multiple fault models are essential
Combination of tests is essential:
 March – SRAM and DRAM
 NPSF -- DRAM
 DC Parametric -- Both
 AC Parametric -- Both
Inductive Fault Analysis is now required
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
138
Analog Test
January 8, 2002 (T5)
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139
Mixed-Signal Testing
Problem
January 8, 2002 (T5)
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140
Differences from Digital
Testing


Size not a problem – at most 100 components
Much harder analog device modeling
 No widely-accepted analog fault model
 Infinite signal range
 Tolerances depend on process and
measurement error
 Tester (ATE) introduces measurement error
 Digital / analog substrate coupling noise
 Absolute component tolerances +/- 20%,
relative +/- 0.1%
 Multiple analog fault model mandatory
 No unique signal flow direction
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
141
Present-Day Analog
Testing Methods

Specification-based (functional) tests
 Main method for analog – tractable and
does not need an analog fault model
 Intractable for digital -- # tests is huge


Structural ATPG – used for digital, just
beginning to be used for analog (exists)
Separate test for functionality and timing
not possible in analog circuit
 Possible in digital circuit
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
142
Definitions









ADC – A/D converter
ATE – Automatic Test Equipment
DAC – D/A converter
DFT – Discrete Fourier Transform
DUT – Device-Under-Test
FFT – Fast Fourier Transform
Glitch Area -- area in DAC output of glitching
pulses
Jitter – Low-level electrical noise – corrupts
LSB’s, especially prevalent on converter
clocking circuits
ks/s – Kilo-samples/sec
January 8, 2002 (T5)
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143
More Definitions







LSB -- Least Significant Bit (of converter)
Measurement – Result of measuring O/P
analog parameter and quantifying it
Measurement Error – Introduced by
measurement process
Non-Deterministic Device – All analog
circuit measurements are not repeatable
due to DUT or tester measurement noise
Phase-Locked-Loop – Clock circuit with
feedback to keep desired signal phase
Settling Time -- Time for DAC
reconstruction filter to settle
Test – Combination of analog stimulus,
measurement of voltage or current, with a
measurement error tolerance
January 8, 2002 (T5)
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144
DSP Tester Concept
© 1987 IEEE
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
145
Waveform Synthesis
© 1987 IEEE
Needs sin x / x (sinc) correction – Finite
sample width
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
146
Waveform Sampling
© 1987 IEEE
Sampling rate > 100 ks/s
January 8, 2002 (T5)
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147
ATE Clock Generator
WS = waveform source
January 8, 2002 (T5)
WM = waveform measurement
Electronic Testing: Agrawal & Bushnell
148
A/D and D/A Test
Parameters



A/D -- Uncertain map from input domain voltages
into digital value (not so in D/A)
 Two converters are NOT inverses
Transmission parameters affect multi-tone tests
 Gain, signal-to-distortion ratio, intermodulation
distortion, noise power ratio, differential phase
shift, envelop delay distortion
Intrinsic parameters – Converter specifications
 Full scale range (FSR), gain, # bits, static
linearity (differential and integral), maximum
clock rate, code format, settling time (D/A),
glitch area (D/A)
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
149
Ideal Transfer Functions
A/D Converter
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
D/A Converter
150
Offset Error
January 8, 2002 (T5)
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151
Gain Error
January 8, 2002 (T5)
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152
D/A Transfer Function
Non-Linearity Error
January 8, 2002 (T5)
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153
Flash A/D Converter
January 8, 2002 (T5)
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154
Differential Linearity Error
 Differential
linearity function – How each code
step differs from ideal or average step (by code
number), as fraction of LSB
 Subtract average count for each code tally,
express that in units of LSBs
 Repeat test waveform 100 to 150 times, use
slow triangle wave to increase resolution
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
155
Linear Histogram and
DLE of 8-bit ADC
© 1987 IEEE
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
156
D/A Differential Test
Fixture
© 1987 IEEE
Measure Vy – Vx difference, not absolute Vx or Vy
January 8, 2002 (T5)
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157
Summary





DSP-based tester has:
 Waveform Generator
 Waveform Digitizer
 High frequency clock with dividers for
synchronization
A/D and D/A Test Parameters
 Transmission
 Intrinsic
A/D and D/A Faults: offset, gain, non-linearity
errors
 Measured by DLE, ILE, DNL, and INL
A/D Test Histograms – static linear and sinusoidal
D/A Test –- Differential Test Fixture
January 8, 2002 (T5)
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158
DSP-Based Testing

Quantization Error – Introduced into
measured signal by discrete sampling

Quantum Voltage – Corresponds to flip of
LSB of converter




Single-Tone Test -- Test of DUT using only
one sinusoidal tone
Tone – Pure sinusoid of f, A, and phase f
Transmission (Performance) Parameter -indicates how channel with embedded
analog circuit affects multi-tone test signal
UTP – Unit test period: joint sampling
period for analog stimulus and response
January 8, 2002 (T5)
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159
Coherent Measurement
Method

Unit Test Period is integration interval P

Has integral # of stimulus periods M

Has integral # of DUT output periods N

Stimulus & sampling are phase locked



To obtain maximum information from
sampling, M and N are relatively prime
Ft – tone frequency
Fs – sampling rate
January 8, 2002 (T5)
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160
CODEC Testing Example

Serial ADC in digital telephone exchange
Sampling rate 8000 s/s
Audio frequency range 300 – 3400 Hz

Ft = 1000 Hz
Fs = 8000 s/s
P = 50 msec
M = 50 cycles
N = 400 samples
Problem: M and N not relatively prime



All samples fall on waveform at certain
phases – sample only 8/255 CODEC steps
January 8, 2002 (T5)
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161
CODEC Testing Solution



Set Fs = 400 ks/s – impossibly fast
Better – Adjust Ft slightly, signal sampled
at different points
Necessary relationships:
Ft = M x D
Fs = N x D
D = 1 / UTP
Ft
M
=
Fs
N
January 8, 2002 (T5)
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162
Good CODEC Parameters
Ft = 1020 Hz
Fs = 8000 s/s
P = UTP = 50 msec
D = 20 Hz
M = 51 cycles
N = 400 samples
 M and N now relatively prime

All samples fall on waveform at different
phases – samples all CODEC steps
January 8, 2002 (T5)
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163
Unit Test Period
© 1987 IEEE
January 8, 2002 (T5)
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164
Spectral Test of A/D
Converter
© 1987 IEEE
January 8, 2002 (T5)
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165
Bad A/D Converter Test
© 1987 IEEE
January 8, 2002 (T5)
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166
Good A/D Converter Test
© 1987 IEEE
January 8, 2002 (T5)
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167
Spectral DSP-Based Testing
Components
© 1987 IEEE
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
168
Correlation Model
© 1987 IEEE
 Cross-correlation – compare 2 different signals
 Autocorrelation – compare 1 signal with itself
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
169
Fourier Voltmeter
st
1 Principle
© 1987 IEEE
For signals A and B, if P is infinite, R = 0. If P
is finite and contains integer # cycles of
both A and B, then cross-correlation R = 0,
regardless of phase or amplitude
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
170
Fourier Voltmeter
nd
2 Principle
© 1987 IEEE
If signals A and B of same f are 90o out of
phase, and P contains an integer J # of
signal cycles, then cross-correlation R = 0,
regardless of amplitude or starting point
January 8, 2002 (T5)
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171
Conceptual Discrete Fourier
Voltmeter
© 1987 IEEE
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
172
A/D Converter Spectrum
© 1987 IEEE
Audio source at 1076 Hz sampled at 44.1 kHz
January 8, 2002 (T5)
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173
Coherent Multi-Tone
Testing
© 1987 IEEE
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
174
Single-Tone Test Example
© 1987 IEEE
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
175
Multi-Tone Test Example
© 1987 IEEE
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
176
Total Harmonic Distortion
(THD)

Measures energy appearing in harmonics
(H2, H3, …) of fundamental tone H1 as % of
energy in the fundamental frequency in
response spectrum
H2

THD =
10
10
10
+ 10
+ … + 10 0
10
H1
10
January 8, 2002 (T5)
H1
H3
20
Electronic Testing: Agrawal & Bushnell
177
DSP Testing Summary


Analog testing greatly increasing in
importance
 System-on-a-chip
 Wireless
 Personal computer multi-media
 Automotive electronics
 Medicine
 Internet telephony
 CD players and audio electronics
Analog testing NOT deterministic like digital
 Statistical testing process, electrical noise
January 8, 2002 (T5)
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178
Delay Test
January 8, 2002 (T5)
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179
Delay Test Definition



A circuit that passes delay test must
produce correct outputs when inputs are
applied and outputs observed with
specified timing.
For a combinational or synchronous
sequential circuit, delay test verifies the
limits of delay in combinational logic.
Delay test problem for asynchronous
circuits is complex and not well
understood.
January 8, 2002 (T5)
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180
Digital Circuit Timing
Input
Signal
changes
Transient
region
Comb.
logic
Synchronized
With clock
Outputs
Inputs
Output
Observation
instant
time
Clock period
January 8, 2002 (T5)
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181
Circuit Delays

Switching or inertial delay is the interval between
input change and output change of a gate:




Propagation or interconnect delay is the time a
transition takes to travel between gates:



Depends on input capacitance, device (transistor)
characteristics and output capacitance of gate.
Also depends on input rise or fall times and states of
other inputs (second-order effects).
Approximation: fixed rise and fall delays (or min-max
delay range, or single fixed delay) for gate output.
Depends on transmission line effects (distributed R, L,
C parameters, length and loading) of routing paths.
Approximation: modeled as lumped delays for gate
inputs.
See Section 5.3.5 for timing models.
January 8, 2002 (T5)
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182
Event Propagation Delays
Single lumped inertial delay modeled for each gate
PI transitions assumed to occur without time skew
Path P1
1
0
13
P2
0
0
January 8, 2002 (T5)
2
1
3
2
246
P3
5
Electronic Testing: Agrawal & Bushnell
183
Robust Test


A robust test guarantees the detection of a
delay fault of the target path, irrespective
of delay faults on other paths.
A robust test is a combinational vector-pair,
V1, V2, that satisfies following conditions:




Produce real events (different steady-state
values for V1 and V2) on all on-path signals.
All on-path signals must have controlling
events arriving via the target path.
A robust test is also a non-robust test.
Concept of robust test is general – robust
tests for other fault models can be defined.
January 8, 2002 (T5)
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184
A Five-Valued Algebra



Signal States: S0, U0 (F0), S1, U1 (R1), XX.
On-path signals: F0 and R1.
Off-path signals: F0=U0 and R1=U1.
Input 1
S0
U0
S1
U1
XX
S0 U0
S1
S0 S0 S0
S0 U0 U0
S0 U0 S1
S0 U0 U1
S0 U0 XX
NOT
January 8, 2002 (T5)
U1
XX
S0 U0
OR
S0 S0
U0 U0
U1 XX
U1 XX
XX XX
Input 2
Input 2
AND
Input 1
S0 S0
U0 U0
S1 S1
U1 U1
XX XX
S0
Input
U0 S1 U1
XX
S1
U1
XX
S0
U0
Electronic Testing: Agrawal & Bushnell
U0
U0
S1
U1
XX
S1
U1
XX
S1 U1 XX
S1 U1 XX
S1 S1 S1
S1 U1 U1
S1 U1 XX
Ref.:
Lin-Reddy
IEEETCAD-87
185
Non-Robust Test Generation
Fault
P2 – rising transition through path P2 has no robust test.
C. Set input of AND gate to
propagate R1 to output
XX U1
R1
D. R1 propagates through
OR gate since off-path
input is U0
R1
Path P2
A. Place R1 at
path origin
R1
R1
R1
U1
U0
Static sensitization:
XX
U0
Non-robust test requires
S0=U0, S1=U1
B. Propagate R1 through OR gate;
interpreted as U1 on off-path signal;
propagates as U0 through NOT gate
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
Non-robust test:
U1, R1, U0
186
Path-Delay Faults (PDF)




Two PDFs (rising and falling transitions) for each physical
path.
Total number of paths is an exponential function of gates.
Critical paths, identified by static timing analysis (e.g.,
Primetime from Synopsys), must be tested.
PDF tests are delay-independent. Robust tests are
preferred, but some paths have only non-robust tests.
Three types of PDFs (Gharaybeh, et al., JETTA (11), 1997):




Singly-testable PDF – has a non-robust or robust test.
Multiply-testable PDF – a set of singly untestable faults
that has a non-robust or robust test. Also known as
functionally testable PDF.
Untestable PDF – a PDF that is neither singly nor multiply
testable.
A singly-testable PDF has at least one single-input change
(SIC) non-robust test.
January 8, 2002 (T5)
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187
Slow-Clock Test
Input
latches
Combinational
circuit
Input
test clock
Test
clock
period
Rated
clock
period
Output
latches
Output
test clock
Input
test clock
Output
test clock
V1
applied
January 8, 2002 (T5)
V2
applied Output
latched
Electronic Testing: Agrawal & Bushnell
188
Normal-Scan Test
V2 states generated, (A) by one-bit scan shift of V1, or
(B) by V1 applied in functional mode.
Combinational
V1 PIs
applied
PO
Scanin
Gen. V2
V1 states states
circuit
SCANOUT
CK TC
Slow clock
SFF
SFF
SCANIN
TC
(A)
CK: system clock
TC: test control
SFF: scan flip-flop
Electronic Testing: Agrawal & Bushnell
Result
scanout
Scan mode
Normal mode
Scan mode
Slow CK
period
TC
(B) Scan mode
Path
tested
Rated
CK period
Scan mode
CK TC
January 8, 2002 (T5)
V2 PIs
applied
Normal
mode
PI
Result
latched
189
t
Variable-Clock Sequential
Test
Off-path
flip-flop
PI
PI
PI
0
T
T
1
n-2
1
PO
PI
PI
1
T
n-1
2
PO
PI
PO
Initialization sequence
(slow clock)
1
T
n
1
2
2
0
D
PO
Path
activation
(rated
Clock)
T
n+1
PO
T
n+m
PO
Fault effect
propagation
sequence
(slow clock)
Note: Slow-clock makes the circuit fault-free in the presence of
delay faults.
January 8, 2002 (T5)
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190
At-Speed Test



At-speed test means application of test vectors at
the rated-clock speed.
Two methods of at-speed test.
External test:



Vectors may test one or more functional critical
(longest delay) paths and a large percentage
(~100%) of transition faults.
High-speed testers are expensive.
Built-in self-test (BIST):




Hardware-generated random vectors applied to
combinational or sequential logic.
Only clock is externally supplied.
Non-functional paths that are longer than the
functional critical path can be activated and cause
a good circuit to fail.
Some circuits have initialization problem.
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Timing Design & Delay Test

Timing simulation:




Critical paths are identified by static (vector-less)
timing analysis tools like Primetime (Synopsys).
Timing or circuit-level simulation using designergenerated functional vectors verifies the design.
Layout optimization: Critical path data are used
in placement and routing. Delay parameter
extraction, timing simulation and layout are
repeated for iterative improvement.
Testing: Some form of at-speed test is
necessary. PDFs for critical paths and all
transition faults are tested.
January 8, 2002 (T5)
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Summary





Path-delay fault (PDF) models distributed delay
defects. It verifies the timing performance of a
manufactured circuit.
Transition fault models spot delay defects and is
testable by modified stuck-at fault tests.
Variable-clock method can test delay faults but the
test time can be long.
Critical paths of non-scan sequential circuits can be
effectively tested by rated-clock tests.
Delay test methods (including BIST) for non-scan
sequential circuits using slow ATE require
investigation:



Suppression of non-functional path activation in BIST.
Difficulty of rated-clock PDF test generation.
Long sequences of variable-clock tests.
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IDDQ Test
January 8, 2002 (T5)
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Basic Principle of IDDQ
Testing
 Measure IDDQ current through Vss bus
January 8, 2002 (T5)
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Capacitive Coupling of
Floating Gates





January 8, 2002 (T5)
Cpb – capacitance from
poly to bulk
Cmp – overlapped metal
wire to poly
Floating gate voltage
depends on capacitances
and node voltages
If nFET and pFET get
enough gate voltage to
turn them on, then IDDQ
test detects this defect
K is the transistor gain
Electronic Testing: Agrawal & Bushnell
196
Bridging Faults S1 – S5




Caused by absolute short
(< 50 W) or higher R
Segura et al. evaluated
testing of bridges with 3
CMOS inverter chain
IDDQRb tests fault when
Rb > 50 KW or
0  Rb  100 KW
Largest deviation when
Vin = 5 V bridged nodes at
opposite logic values
January 8, 2002 (T5)
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Delay Faults



Most random CMOS defects cause a timing
delay fault, not catastrophic failure
Many delay faults detected by IDDQ test –
late switching of logic gates keeps IDDQ
elevated
Delay faults not detected by IDDQ test
 Resistive via fault in interconnect
 Increased transistor threshold voltage
fault
January 8, 2002 (T5)
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Leakage Faults

Gate oxide shorts cause leaks between gate &
source or gate & drain

Mao and Gulati leakage fault model:
 Leakage path flags: fGS, fGD, fSD, fBS, fBD, fBG
G = gate, S = source, D = drain, B = bulk

Assume that short does not change logic values
January 8, 2002 (T5)
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Weak Faults



nFET passes logic 1 as 5 V – Vtn
pFET passes logic 0 as 0 V + |Vtp|
Weak fault – one device in C-switch does not
turn on
 Causes logic value degradation in C-switch
January 8, 2002 (T5)
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Gate Oxide Short
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Quietest Results
Ckt.
# of
# of
%
Leakage
Tran- Leakage Selected
Fault
Sistors Faults
Vectors Coverage
7584
39295
0.5 %
94.84 %
42373 220571
0.99 %
90.50 %
1
2
Ckt.
1
2
January 8, 2002 (T5)
# of
Weak
Faults
1923
1497
%
Weak
Selected
Fault
Vectors Coverage
0.35 %
85.3 %
0.21 %
87.64 %
Electronic Testing: Agrawal & Bushnell
202
Sematech Results
Scan-based Stuck-at

Test process: Wafer Test
Package Test
Burn-In & Retest
Characterize & Failure
Analysis
Data for devices failing some, but not all, tests.
IDDQ (5 mA limit)
pass
fail
pass
fail
January 8, 2002 (T5)
pass pass
6
14
0
6
1
52
36
pass fail
fail
1463
34
13
1251
pass
fail
7 pass
1 pass
8
fail
fail
fail
Functional
Electronic Testing: Agrawal & Bushnell
Scan-based delay

203
Summary




IDDQ tests improve reliability, find defects
causing:
 Delay, bridging, weak faults
 Chips damaged by electro-static discharge
No natural breakpoint for current threshold
 Get continuous distribution – bimodal
would be better
Conclusion: now need stuck-fault, IDDQ, and
delay fault testing combined
Still uncertain whether IDDQ tests will remain
useful as chip feature sizes shrink further
January 8, 2002 (T5)
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Part III
DESIGN FOR
TESTABILITY
Scan Design
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Definition


Design for testability (DFT) refers to those design
techniques that make test generation and test
application cost-effective.
DFT methods for digital circuits:
 Ad-hoc methods
 Structured methods:





Scan
Partial Scan
Built-in self-test (BIST)
Boundary scan
DFT method for mixed-signal circuits:

Analog test bus
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Ad-Hoc DFT Methods

Good design practices learnt through experience are
used as guidelines:









Avoid asynchronous (unclocked) feedback.
Make flip-flops initializable.
Avoid redundant gates. Avoid large fanin gates.
Provide test control for difficult-to-control signals.
Avoid gated clocks.
...
Consider ATE requirements (tristates, etc.)
Design reviews conducted by experts or design auditing
tools.
Disadvantages of ad-hoc DFT methods:



Experts and tools not always available.
Test generation is often manual with no guarantee of
high fault coverage.
Design iterations may be necessary.
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Scan Design
 Circuit is designed using pre-specified design

rules.
Test structure (hardware) is added to the
verified design:



Add a test control (TC) primary input.
Replace flip-flops by scan flip-flops (SFF) and connect
to form one or more shift registers in the test mode.
Make input/output of each scan shift register
controllable/observable from PI/PO.
 Use combinational ATPG to obtain tests for all

testable faults in the combinational logic.
Add shift register tests and convert ATPG tests
into scan sequences for use in manufacturing
test.
January 8, 2002 (T5)
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Scan Design Rules




Use only clocked D-type of flip-flops for all
state variables.
At least one PI pin must be available for test;
more pins, if available, can be used.
All clocks must be controlled from PIs.
Clocks must not feed data inputs of flip-flops.
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Scan Flip-Flop (SFF)
Master latch
D
Slave latch
TC
Q
Logic
overhead
MUX
SD
Q
CK
D flip-flop
CK
TC
January 8, 2002 (T5)
Master open Slave open
Normal mode, D selected
t
Scan mode, SD selected
Electronic Testing: Agrawal & Bushnell
t
210
Level-Sensitive Scan-Design
Flip-Flop (LSSD-SFF)
Master latch
Slave latch
D
Q
MCK
Q
D flip-flop
SD
MCK
Logic
TCK
TCK
January 8, 2002 (T5)
MCK
TCK
Scan
mode
overhead
Normal
mode
SCK
SCK
t
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211
Adding Scan Structure
PI
PO
Combinational
SFF
logic
SFF
SCANOUT
SFF
TC or TCK
SCANIN
January 8, 2002 (T5)
Not shown: CK or
MCK/SCK feed all
SFFs.
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Comb. Test Vectors
PI
I1
I2
January 8, 2002 (T5)
O2
Combinational
SCANIN
TC
Presen
t
state
O1
SCANOUT
logic
S1
S2
Electronic Testing: Agrawal & Bushnell
PO
N1
N2
Next
state
213
Comb. Test Vectors
SCANIN
I2
I1
PI
S1
S2
TC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
PO
SCANOUT
Don’t care
or random
bits
1 0000000
O2
O1
N1
N2
Sequence length = (ncomb + 1) nsff + ncomb clock periods
ncomb = number of combinational vectors
nsff = number of scan flip-flops
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Testing Scan Register





Scan register must be tested prior to
application of scan test sequences.
A shift sequence 00110011 . . . of length
nsff+4 in scan mode (TC=0) produces 00, 01,
11 and 10 transitions in all flip-flops and
observes the result at SCANOUT output.
Total scan test length:
(ncomb
+ 2) nsff + ncomb + 4 clock periods.
Example: 2,000 scan flip-flops, 500 comb.
vectors, total scan test length ~ 106 clocks.
Multiple scan registers reduce test length.
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Scan Overheads



IO pins: One pin necessary.
Area overhead:
 Gate overhead = [4 nsff/(ng+10nff)] x 100%,
where ng = comb. gates; nff = flip-flops;
Example – ng = 100k gates, nff = 2k flip-flops,
overhead = 6.7%.
 More accurate estimate must consider scan
wiring and layout area.
Performance overhead:
 Multiplexer delay added in combinational
path; approx. two gate-delays.
 Flip-flop output loading due to one additional
fanout; approx. 5-6%.
January 8, 2002 (T5)
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ATPG Example: S5378
Original
Number of combinational gates
Number of non-scan flip-flops (10 gates each)
Number of scan flip-flops (14 gates each)
Gate overhead
Number of faults
PI/PO for ATPG
Fault coverage
Fault efficiency
CPU time on SUN Ultra II, 200MHz processor
Number of ATPG vectors
Scan sequence length
January 8, 2002 (T5)
Electronic Testing: Agrawal & Bushnell
2,781
179
0
0.0%
4,603
35/49
70.0%
70.9%
5,533 s
414
414
Full-scan
2,781
0
179
15.66%
4,603
214/228
99.1%
100.0%
5s
585
105,662
217
Summary

Scan is the most popular DFT technique:




Advantages:





Rule-based design
Automated DFT hardware insertion
Combinational ATPG
Design automation
High fault coverage; helpful in diagnosis
Hierarchical – scan-testable modules are easily
combined into large scan-testable systems
Moderate area (~10%) and speed (~5%) overheads
Disadvantages:


Large test data volume and long test time
Basically a slow speed (DC) test
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Built-In Self-Test
(BIST)
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Economics – BIST Costs
 Chip area overhead for:
 Test





controller
 Hardware pattern generator
 Hardware response compacter
 Testing of BIST hardware
Pin overhead -- At least 1 pin needed to
activate BIST operation
Performance overhead – extra path delays due
to BIST
Yield loss – due to increased chip area or more
chips In system because of BIST
Reliability reduction – due to increased area
Increased BIST hardware complexity –
happens when BIST hardware is made testable
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220
BIST Benefits


Faults tested:
 Single combinational / sequential stuck-at
faults
 Delay faults
 Single stuck-at faults in BIST hardware
BIST benefits
 Reduced testing and maintenance cost
 Lower test generation cost
 Reduced storage / maintenance of test
patterns
 Simpler and less expensive ATE
 Can test many units in parallel
 Shorter test application times
 Can test at functional
system speed
January 8, 2002 (T5)
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221
BIST Process


Test controller – Hardware that activates self-
test simultaneously on all PCBs
Each board controller activates parallel chip BIST
Diagnosis effective only if very high fault
coverage
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BIST Architecture

Note: BIST cannot test wires and transistors:
 From PI pins to Input MUX
 From POs to output pins
January 8, 2002 (T5)
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Example External XOR
LFSR

Characteristic polynomial f (x) = 1 + x + x3
(read taps from right to left)
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External XOR LFSR

Pattern sequence for example LFSR (earlier):
X0
X1
X2


1 0 0 1 0 1 1 1 0
0 0 1 0 1 1 1 0 0
0 1 0 1 1 1 0 0 1
…
Always have 1 and xn terms in polynomial
Never repeat an LFSR pattern more than 1 time –
Repeats same error vector, cancels fault effect
X0 (t + 1)
X1 (t + 1)
X2 (t + 1)
January 8, 2002 (T5)
=
0 1 0
0 0 1
1 1 0
Electronic Testing: Agrawal & Bushnell
X 0 (t)
X 1 (t)
X 2 (t)
225
Response Compaction



Severe amounts of data in CUT response to
LFSR patterns – example:
 Generate 5 million random patterns
 CUT has 200 outputs
 Leads to: 5 million x 200 = 1 billion bits
response
Uneconomical to store and check all of these
responses on chip
Responses must be compacted
January 8, 2002 (T5)
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226
Definitions





Aliasing – Due to information loss, signatures
of good and some bad machines match
Compaction – Drastically reduce # bits in
original circuit response – lose information
Compression – Reduce # bits in original
circuit response – no information loss – fully
invertible (can get back original response)
Signature analysis – Compact good machine
response into good machine signature.
Actual signature generated during testing,
and compared with good machine signature
Transition Count Response Compaction –
Count # transitions from 0
1 and 1
0 as
a signature
January 8, 2002 (T5)
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227
LFSR for Response
Compaction





Use cyclic redundancy check code (CRCC)
generator (LFSR) for response compacter
Treat data bits from circuit POs to be compacted
as a decreasing order coefficient polynomial
CRCC divides the PO polynomial by its
characteristic polynomial
 Leaves remainder of division in LFSR
 Must initialize LFSR to seed value (usually 0)
before testing
After testing – compare signature in LFSR to
known good machine signature
Critical: Must compute good machine signature
January 8, 2002 (T5)
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Example Modular LFSR
Response Compacter

January 8, 2002 (T5)
LFSR seed value is “00000”
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229
Polynomial Division
Inputs
Initial State
1
0
0
Logic
0
Simulation:
1
0
1
0
X0 X1 X2 X3 X4
0
1
0
0
0
1
1
1
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
Logic simulation: Remainder = 1 + x2 + x3
0 1 0 1 0 0 0 1
0 . x0 + 1 . x1 + 0 . x2 + 1 . x3 + 0 . x4 + 0 . x5 + 0 . x6
+ 1 . x7
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Symbolic Polynomial
Division
x5 + x3 + x + 1
remainder
x2 + 1
+
x7
x7 + x5 +
x5
x5 +
x3
+x
x3 + x2
+ x2 + x
x3
+x +1
x3 + x2
+1
Remainder matches that from logic simulation
of the response compacter!
January 8, 2002 (T5)
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Multiple-Input Signature
Register (MISR)


Problem with ordinary LFSR response
compacter:
 Too much hardware if one of these is put on
each primary output (PO)
Solution: MISR – compacts all outputs into one
LFSR
 Works because LFSR is linear – obeys
superposition principle
 Superimpose all responses in one LFSR –
final remainder is XOR sum of remainders of
polynomial divisions of each PO by the
characteristic polynomial
January 8, 2002 (T5)
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Modular MISR Example
X0 (t + 1)
X1 (t + 1)
X2 (t + 1)
January 8, 2002 (T5)
=
0 0 1
1 0 1
0 1 0
X 0 (t)
X 1 (t) +
X 2 (t)
Electronic Testing: Agrawal & Bushnell
d0 (t)
d1 (t)
d2 (t)
233
Aliasing Theorems

Theorem 15.1: Assuming that each circuit PO dij
has probability p of being in error, and that all
outputs dij are independent, in a k-bit MISR,
Pal = 1/(2k), regardless of initial condition of
MISR. Not exactly true – true in practice.

Theorem 15.2: Assuming that each PO dij has
probability pj of being in error, where the pj
probabilities are independent, and that all
outputs dij are independent, in a k-bit MISR,
Pal = 1/(2k), regardless of the initial condition.
January 8, 2002 (T5)
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234
Built-in Logic Block
Observer (BILBO)

Combined functionality of D flip-flop, pattern
generator, response compacter, & scan chain
 Reset all FFs to 0 by scanning in zeros
January 8, 2002 (T5)
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235
Example BILBO Usage

SI – Scan In
SO – Scan Out
Characteristic polynomial: 1 + x + … + xn

CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR

CUT B:


January 8, 2002 (T5)
BILBO1 is LFSR, BILBO2 is MISR
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236
Circuit Initialization


Full-scan BIST – shift in scan chain seed before starting
BIST
Partial-scan BIST – critical to initialize all FFs before
BIST starts
 Otherwise we clock X’s into MISR and signature is
not unique and not repeatable

Discover initialization problems by:
1. Modeling all BIST hardware
2. Setting all FFs to X’s
3. Running logic simulation of CUT with BIST hardware
January 8, 2002 (T5)
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237
Circuit Initialization
(continued)



If MISR finishes with BIST cycle with X’s in
signature, Design-for-Testability initialization
hardware must be added
Add MS (master set) or MR (master reset)
lines on flip-flops and excite them before
BIST starts
Otherwise:
1. Break all cycles of FF’s
2. Apply a partial BIST synchronizing
sequence to initialize all FF’s
3. Turn on the MISR to compact the response
January 8, 2002 (T5)
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238
Test Point Insertion

BIST does not detect all faults:
 Test patterns not rich enough to test all
faults


Modify circuit after synthesis to improve
signal controllability
Observability addition – Route internal signal
to extra FF in MISR or XOR into existing FF in
MISR
January 8, 2002 (T5)
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239
SRAM BIST with MISR

Use MISR to compress memory outputs

Control aliasing by repeating test:
 With different MISR feedback polynomial
 With RAM test patterns in reverse order

March test:
{

(w Address);
(r Address);
(w Address);
(r Address);
(r Address);
(w Address);
(r Address);
(r Address) }
Not proven to detect coupling or address
decoder faults
January 8, 2002 (T5)
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240
BIST System with MISR
January 8, 2002 (T5)
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241
Summary



LFSR pattern generator and MISR response
compacter – preferred BIST methods
BIST has overheads: test controller, extra
circuit delay, Input MUX, pattern generator,
response compacter, DFT to initialize circuit &
test the test hardware
BIST benefits:
 At-speed testing for delay & stuck-at faults
 Drastic ATE cost reduction
 Field test capability
 Faster diagnosis during system test
 Less effort to design testing process
 Shorter test application times
January 8, 2002 (T5)
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IEEE 1149.1
Boundary Scan Standard
January 8, 2002 (T5)
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243
Motivation for Standard

Bed-of-nails printed circuit board tester gone
 We put components on both sides of




PCB &
replaced DIPs with flat packs to reduce
inductance
 Nails would hit components
Reduced spacing between PCB wires
 Nails would short the wires
PCB Tester must be replaced with built-in test
delivery system -- JTAG does that
Need standard System Test Port and Bus
Integrate components from different vendors
 Test bus identical for various components
 One chip has test hardware for other chips
January 8, 2002 (T5)
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244
Purpose of Standard






Lets test instructions and test data be serially
fed into a component-under-test (CUT)
 Allows reading out of test results
 Allows RUNBIST command as an instruction
 Too many shifts to shift in external tests
JTAG can operate at chip, PCB, & system levels
Allows control of tri-state signals during testing
Lets other chips collect responses from CUT
Lets system interconnect be tested separately
from components
Lets components be tested separately from
wires
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System Test Logic
January 8, 2002 (T5)
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Instruction Register
Loading with JTAG
January 8, 2002 (T5)
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System View of Interconnect
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Boundary Scan Chain View
January 8, 2002 (T5)
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249
Elementary Boundary
Scan Cell
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Serial Board / MCM Scan
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Parallel Board / MCM Scan
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Tap Controller Signals

Test Access Port (TAP) includes these signals:
 Test Clock Input (TCK) -- Clock for test logic
Can run at different rate from system clock
Test Mode Select (TMS) -- Switches system
from functional to test mode
Test Data Input (TDI) -- Accepts serial test
data and instructions -- used to shift in
vectors or one of many test instructions
Test Data Output (TDO) -- Serially shifts out
test results captured in boundary scan chain
(or device ID or other internal registers)
Test Reset (TRST) -- Optional asynchronous
TAP controller reset





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SAMPLE / PRELOAD
Instruction -- SAMPLE
Purpose:
1. Get snapshot of normal chip output signals
2. Put data on bound. scan chain before next instr.
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SAMPLE / PRELOAD
Instruction -- PRELOAD
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EXTEST Instruction

Purpose: Test off-chip circuits and boardlevel interconnections
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INTEST Instruction

Purpose:
1. Shifts external test patterns onto component
2. External tester shifts component responses out
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RUNBIST Instruction





Purpose: Allows you to issue BIST command to
component through JTAG hardware
Optional instruction
Lets test logic control state of output pins
1. Can be determined by pin boundary scan cell
2. Can be forced into high impedance state
BIST result (success or failure) can be left in
boundary scan cell or internal cell
 Shift out through boundary scan chain
May leave chip pins in an indeterminate state
(reset required before normal operation
resumes)
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CLAMP Instruction




Purpose: Forces component output signals
to be driven by boundary-scan register
Bypasses the boundary scan chain by
using the one-bit Bypass Register
Optional instruction
May have to add RESET hardware to
control on-chip logic so that it does not
get damaged (by shorting 0’s and 1’s onto
an internal bus, etc.)
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IDCODE Instruction



Purpose: Connects the component device
identification register serially between TDI
and TDO
 In the Shift-DR TAP controller state
Allows board-level test controller or
external tester to read out component ID
Required whenever a JEDEC identification
register is included in the design
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Device ID Register -JEDEC Code
MSB
31
28
Version
(4 bits)
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27 12
Part
Number
(16 bits)
11
1
Manufacturer
Identity
(11 bits)
Electronic Testing: Agrawal & Bushnell
LSB
0
‘1’
(1 bit)
261
USERCODE Instruction





Purpose: Intended for user-programmable
components (FPGA’s, EEPROMs, etc.)
 Allows external tester to determine user
programming of component
Selects the device identification register as
serially connected between TDI and TDO
User-programmable ID code loaded into device
identification register
 On rising TCK edge
Switches component test hardware to its
system function
Required when Device ID register included on
user-programmable component
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HIGHZ Instruction




Purpose: Puts all component output pin signals
into high-impedance state
Control chip logic to avoid damage in this mode
May have to reset component after HIGHZ runs
Optional instruction
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BYPASS Instruction

Purpose: Bypasses scan chain with 1-bit register
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Summary

Boundary Scan Standard has become
absolutely essential - No longer possible to test printed circuit
boards with bed-of-nails tester
 Not possible to test multi-chip modules
at all without it
 Supports BIST, external testing with
Automatic Test Equipment, and
boundary scan chain reconfiguration as
BIST pattern generator and response
compacter
 Now getting widespread usage
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IEEE 1149.4 Analog Test
Bus
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Analog Test Bus


PROs:
 Usable with digital JTAG boundary scan
 Adds analog testability – both controllability
and observability
 Eliminates large area needed for analog test
points
CONs:
 May have a 5 % measurement error
 C-switch sampling devices couple all probe
points capacitively, even with test bus off –
requires more elaborate (larger) switches
 Stringent limit on how far data can move
through the bus before it must be digitized
to retain accuracy
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Analog Test Bus Diagram
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Analog Boundary Module
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Chaining of 1149.4 ICs
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System Test
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A System and Its Testing


A system is an organization of components
(hardware/software parts and subsystems) with
capability to perform useful functions.
Functional test verifies integrity of system:




Checks for presence and sanity of subsystems
Checks for system specifications
Executes selected (critical) functions
Diagnostic test isolates faulty part:



For field maintenance isolates lowest replaceable
unit (LRU), e.g., a board, disc drive, or I/O subsystem
For shop repair isolates shop replaceable unit (SRU),
e.g., a faulty chip on a board
Diagnostic resolution is the number of suspected
faulty units identified by test; fewer suspects mean
higher resolution
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Functional Test




All or selected (critical) operations executed
with non-exhaustive data.
Tests are a subset of design verification
tests (test-benches).
Software test metrics used: statement,
branch and path coverages; provide low
(~70%) structural hardware fault coverage.
Examples:


Microprocessor test – all instructions with
random data (David, 1998).
Instruction-set fault model – wrong instruction is
executed (Thatte and Abraham, IEEETC-1980).
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Gate-Level Diagnosis
Karnaugh map
Logic circuit
(shaded squares are true outputs)
b
a
b
c
d
e
T2
a
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T4
T3
Stuck-at fault tests:
T1 = 010
T2 = 011
T3 = 100
T4 = 110
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T1
c
274
Gate Replacement Fault
Karnaugh map
Faulty circuit
(faulty output shown in red)
(OR replaced by AND)
a
b
c
b
d
e
T2
a
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T4
T3
Stuck-at fault tests:
T1 = 010 (pass)
T2 = 011 (fail)
T3 = 100 (pass)
T4 = 110 (fail)
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T1
c
275
Fault Dictionary
Fault
Test syndrome
t1
t2
t3
t4
No fault
0
0
0
0
a0, b0, d0
0
0
0
1
a1
1
0
0
0
b1
0
0
1
0
c0
0
1
0
0
c1, d1, e1
1
0
1
0
e0
0
1
0
1
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a0 : Line a stuckat-0
ti = 0, if Ti passes
= 1, if Ti fails
276
Diagnosis with Dictionary
Dictionary look-up with minimum Hamming distance
Fault
OR
AND
OR-bridge (a,c)
OR
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NOR
Test syndrome
t1
t2
t3
t4
Diagnosis
0
1
0
1
e0
0
0
1
0
b1
1
1
1
1
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c1, d1, e1, e0
277
System Test:
Partitioning for Test



Partition according to test methodology:
 Logic blocks
 Memory blocks
 Analog blocks
Provide test access:
 Boundary scan
 Analog test bus
Provide test-wrappers (also called collars)
for cores.
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Test-Wrapper for a Core


Test-wrapper (or collar) is the logic added around a core
to provide test access to the embedded core.
Test-wrapper provides:
 For each core input terminal



A normal mode – Core terminal driven by host chip
An external test mode – Wrapper element observes core
input terminal for interconnect test
An internal test mode – Wrapper element controls state
of core input terminal for testing the logic inside core
 For each core output terminal



A normal mode – Host chip driven by core terminal
An external test mode – Host chip is driven by wrapper
element for interconnect test
An internal test mode – Wrapper element observes core
outputs for core test
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A Test-Wrapper
from/to
External
Test pins
Scan chain
to/from TAP
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Functional
core outputs
Core
Scan chain
Scan chain
Functional
core inputs
Wrapper
elements
Wrapper
test
controlle
r
280
Overhead Estimate
Rent’s rule: For a logic block the number of gates G
and the number of terminals t are related by
t = K Ga
where 1 < K < 5, and a ~ 0.5.
Assume that block area A is proportional to G, i.e.,
t is proportional to A 0.5. Since test logic is added
to each terminal t,
Test logic added to terminals
Overhead = ------------------------------------------------- ~ A –0.5
A
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DFT Architecture for SOC
Module
N
wrapper
1
Func.
outputs
Func.
inputs
Test
Module
wrapper
Functional
inputs
User defined test access mechanism (TAM)
Test
Test
source
Test
sink
Functional
outputs
Instruction register control
January 8, 2002 (T5)
TDO
TRST
TMS
TCK
SOC inputs
Test access port (TAP)
TDI
Serial instruction data
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SOC outputs
282
Summary



Functional test: verify system hardware, software,
function and performance; pass/fail test with
limited diagnosis; high (~100%) software coverage
metrics; low (~70%) structural fault coverage.
Diagnostic test: High structural coverage; high
diagnostic resolution; procedures use fault
dictionary or diagnostic tree.
SOC design for testability:





Partition SOC into blocks of logic, memory and
analog circuitry, often on architectural boundaries.
Provide external or built-in tests for blocks.
Provide test access via boundary scan and/or
analog test bus.
Develop interconnect tests and system functional
tests.
Develop diagnostic procedures.
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References

M.L. Bushnell and V. D. Agrawal, Essentials

Kluwer Academic Publishers, 2000, ISBN
0-7923-7991-8.
For the material on a course taught by the
authors at Rutgers University, and a
complete bibliography from the above
book, see website:
of Electronic Testing for Digital, Memory
and Mixed-Signal VLSI Circuits, Boston:
http://cm.bell-labs.com/cm/cs/who/va
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