Transcript talk3-7
DSP Based Equalization for 40-Gbps Fiber Optic Communication Shahriar Shahramian Problem & Motivation • At high bit rates (> 10 Gbps) fiber optic channel’s impairments become prominent. • Differential Mode Dispersion (in Multi Mode Fiber) & Polarization Mode Dispersion (in Single Mode Fiber) degrade signal quality over long haul fiber channels. • Equalization techniques are required to achieve high bit rate over fiber optic channels. Problem & Motivation II • Some analog equalization techniques have been shown for 40-Gbps communication. • Another possibility for equalization is digital equalization. • The main challenge of high speed digital equalization is the design of the ADC at such high bit rates. • Provided that high speed ADCs can be built, digital equalization is more accurate and offers more flexibility. DSP Equalizer Block Diagram Optical Fiber Detector & Pre-Amp Ultra Fast ADC (40-GS/s) Adaptive Channel Equalizer Equalized Data Clock Recovery DFE Adaptive Channel Equalizer FFE + Slicer - Flash ADC Block Diagram Input Stage TIA Track & Hold 16 TH DRV INV Data Tree T/H 1 16 S/H Clock Thermometer Code Output Comparators (16) INV INV Latch Clock Tree 16 External Clock 1 16 GAIN Offset Amp. Input Stage THA Block Diagram TIA Track & Hold TH DRV INV T/H Clock Distribution TIA INV INV Output Driver CLK DRV DRV Data Output THA Die Photo Data Input (DC – 20 GHz) DC & Biasing Input • Chip Area: – 1.1mm2 • Technology: – 0.18μm SiGe BiCMOS HBT – 150/155 GHz fT/fmax Clock Input (40 GHz) • Foundry: – Jazz Semiconductor THA Measurement Results • Both data and clock input have been applied single ended. • In Differential mode, the “in phase” clock feedthrough signal is eliminated. OP Diff. Output OP ON Diff. Output THA Measurements II • Two tone signals at the input (separated by 100 MHz) have been used to measure the IM3 output power and the input compression point. • An abstract has been submitted to CSICS 2005 based on this circuit as (to our best knowledge) the world’s fastest THA.