Transcript Ch4 Computer Organization

Computer Organization
Prepared by:
Course:
Professor:
Date:
Anh Q. Vu
CS-147
Sin-Min Lee
Summer - 2001
Computer Organization
Contents (Text Book: page 142 – 158)
1.
2.
3.
4.
5.
6.
7.
8.
9.
Overview
Computer Organization
Definitions - Buses
Computer Organization Diagram
CPU organization Diagram
Memory
Memory Chip Organization
The Instruction Cycle
Supporting Diagrams
(25 minutes)
Computer Organization
“Overview”
The Intel Microprocessor Evolution
Microprocessor
8008
8080
8085
8086
8088
80286
80386
80486
Pentium
Pentium Pro
Pentium III
Pentium 4
Year introduced
1972
1974
1976
1978
1979
1982
1985
1989
1992
1995
1999
2000
# of Transistors
3000
4500
6500
29,000
29,000
130,000
275,000
1.2 million
3.1 million
5.5 million
9.5 million
42 million
Computer Organization
Computer Organization
•
A computer is organized into 3 internal parts:
1. CPU
2. Memory
3. I/O (Input/Output)
Computer Organization
1. CPU
–
–
–
It is the Central Processing Unit of the
computer.
Its function is to execute or process the
information stored in memory.
The CPU is connected to memory and I/O
through strips of wire called bus.
Computer Organization
2. Memory
–
Memory is the big store house of data located
within the main computer outside of the
Microprocessor.
Computer Organization
3. I/O (Input/Output)
–
Input devices provide signals to the CPU.
» Keyboard, Sensors, Switches, etc.
–
Output devices take signals from the CPU and
perform required actions.
» Printers, Monitor, Lights, etc.
Computer Organization
BUS
•
Bus
–
–
–
Bus is a set of wires that connects the CPU to
memory and I/O
It carries information from place to place just as a
street bus carries people from place to place.
There are 3 types of bus
»
»
»
Address bus
Data bus
Control bus
Computer Organization
BUS cont.
a) Address bus
–
–
–
–
Address bus is the set of wires that carries addresses
of memory or I/O only.
For a memory or I/O to be recognized by the CPU it
must be assigned an address.
The assigned address must be unique; no two devices
are allowed to have the same address.
The CPU puts the address on the address bus, and the
decoding circuitry finds the device.
Computer Organization
BUS cont.
b)
Data bus
– Data bus is a set of wires that carries data only.
– After finding the device through the address
bus, the CPU uses the data bus either to get data
or to send data to the device.
Computer Organization
BUS cont.
c)
Control bus
– Control bus is a set of wires that carries control
signals only.
– The control buses are used to provide read or
write signals to the device to indicate if the
CPU is asking or sending information.
Computer Organization
Diagram
Address bus
RAM
ROM
CPU
Data bus
Read/Write
Control bus
Disk
Keyboard
Printer/
Monitor
CPU Internal Organization
Diagram
Control bus signals
Control Unit
Address bus
Control signals
Program Counter
Data Values
Instruction Register
REGISTERS
Control signals
Data values (operands)
ALU
Data bus
Data values (results)
Register A
Register B
Register C
Etc.
MEMORY
Memory
Types of Memory Chips
1. ROM
•
•
Read Only Memory, Not able to write to it.
Non Volatile; Retains data when power is turned-off
2. RAM
•
Random Access Memory, able to read and write to it.
Memory
Types of ROM Chips
•
MROM
–
–
•
Set by manufacturer and cannot be changed
Mostly used on consumer appliances where large quantities are produced.
PROM
–
–
–
(Masked Read Only Memory)
(Programmable Read Only Memory)
Programmable but only once
Programmed by blowing internal fuses
Mostly used for prototypes
Memory
Types of ROM Chips cont.
•
EPROM
(Erasable & Programmable ROM)
» Totally erasable by exposing it to ultra violet light
for over 20 minutes.
» Programmable outside the circuit.
•
EEPROM
(Electrically Erasable & Programmable ROM)
»
»
»
»
•
Electrically erasable.
Able to erase a portion of the memory.
Can be re programmed while in circuit.
Mostly used for computer BIOS
FLASH Memory
» Electrically erased, but it erases the entire memory.
Memory
Types of RAM Chips
•
DRAM
(Dynamic Random Access Memory)
» Widely used as main computer memory
•
SRAM
(Static Random Access Memory)
» Faster than DRAM
» More expensive than DRAM
» Mostly used in Cache memory
•
NVRAM
(Non Volatile Random Access Memory)
» Does not lose data in memory when turned off.
» Contains an internal Lithium battery to retain power
Memory Chip Organization
•
•
The internal organization of ROM and RAM chips are similar.
There are two organizations
1. Linear Organization
2. Two-Dimensional organization
Memory Chip Organization
•
Linear Organization
» It is a simpler form of organization
» Used if few number of memory locations are needed
Memory Chip Internal Linear Organization
of an 8 x 2 ROM chip
01
00
11
10
21
20
A2 A1 A0
0
1
A2
A1
A0
2
3 to 8
Decoder
0
0 0 1
1
0 1 0
2
0 1 1
3
31
30
41
40
1 0 0
4
51
50
1 0 1
5
61
60
1 1 0
6
71
70
1 1 1
7
3
4
5
6
E
0 0 0
7
CE
OE
D1
D0
Memory Chip Organization
•
Two-dimensional Organization
» Used to manage a large number of memory locations
» Allows large memory locations using fewer chips
Memory Chip Internal two-dimensional
Organization of an 8 x 2 ROM chip
01
00
11
10
21
20
31
30
41
40
51
50
61
60
71
70
0
A2
A1
2 to 4
Decoder
1
2
3
E
A0
1 to 2
Decoder
0
1
E
CE
OE
D1
D0
Instruction Cycle
The Instruction Cycle
1. The Fetch cycle
•
Fetch an instruction from memory, then go to the
decode cycle
2. The Decode cycle
•
Decode the instruction – determine which
instruction has been fetched –go to execute cycle for
that instruction.
3. The execute cycle
•
Execute the instruction, then go to fetch cycle and
fetch the next instruction.
The Instruction Cycle
•
The Fetch cycle
»
»
»
»
»
»
»
The CPU puts an address of instruction on the address bus.
The memory decodes the address to access the desired
memory location.
The CPU allows sufficient time for the memory to decode the
address and sends a READ control signal.
The READ signal is a signal on the Control bus which the
CPU sends when it’s ready to read data from memory or I/O
device.
When the READ signal is asserted, the memory puts the
instruction code to be fetched on to the data bus.
The CPU inputs the data and stores it in one of its internal
registers.
The fetch cycle is completed.
The Instruction Cycle
•
The Decode cycle
» The CPU decodes the instruction.
» Each instruction may require a different sequence of
operations to execute the instruction.
» The CPU determines which instruction it is in order to
select the correct sequence of operation to perform.
» This is done entirely within the CPU, it does not use the
system buses.
The Instruction Cycle
•
The Execute cycle
» The CPU executes the instruction.
» The execution may be:
1.
2.
3.
4.
Read/write data to/from memory.
Read/Write data to/from an I/O device.
Perform only operations within the CPU.
Perform some combination of the above.
Sample Diagrams
Fetch, Decode & Execute Cycles
2+3=5 operation
Fetch, Decode & Execute Cycles
2+3=5 operation
Fetch, Decode & Execute Cycles
2+3=5 operation
Fetch, Decode & Execute Cycles
2+3=5 operation
The End
Thanks!!