Transcript Basic Microcomputer Design

Basic Microcomputer Design
Inside the CPU
• Registers – storage locations
• Control Unit (CU) – coordinates the
sequencing of steps involved in executing
machine instructions
• Arithmetic Logic Unit (ALU) - performs
arithmetic and logical operations
• Clock – synchronizes the internal
operations of the CPU with the other
system components
Bus Structure
• Bus - a group of parallel wires that transfer
information from one part of the computer
to another.
– Control Bus – synchronizes the actions of all
of the devices attached to the system bus.
– Address Bus – passes the addresses of
instructions and data between the CPU and
memory (or I/O).
– Data Bus – transfers instructions and data
between the CPU and memory (or I/O).
Bus Sizes
• For the 8086 Processor
– Data Bus – 16 bits (16-bit processor)
– Address Bus – 20 bits (can access 1M of
memory)
The Intel CPU Family
Chip
Date
MHz
4004
4/1971
0.108
8008
4/1972
0.108
8080
4/1974
2-3
8085
4/1976
3-8
8086
6/1978
5-10
8088
6/1979
5-8
80286
2/1982
8-12
80386
10/1985
16-33
80486
4/1989 25-100
Pentium
3/1993 60-233
Pentium Pro 3/1995 150-200
Pentium II
5/1997 233-400
Pentium III
1998
550
Transistors Memory
2,300
3,500
6,000
6,500
29,000
29,000
134,000
275,000
1.2M
3.1M
5.5M
7.5M
9.5M
Notes
640 First microprocessor on a chip
16KB First 8-bit processor
64KB First general-purpose CPU on a chip
64KB
1MB First 16-bit CPU on a chip
1MB Used in IBM PC
16MB Memory protection present
4GB First 32-bit CPU
4GB Built-in 8K cache memory
4GB Two pipelines; later models had MMX
4GB Two levels of cache built in
4GB Pentium Pro plus MMX
Streaming SIMD extensions (SSE)
Notes from Intel Family Chart
• Notice that 386 – Pentium 4 are 32-bit
processors (32-bit data bus – 4 bytes)
• Notice that 386 and beyond have 32-bit
address bus can access (4G of memory
addresses).
Machine Cycle
• Most basic unit of time for machine
instructions
• = the time required for one complete clock
cycle.
• Machine instructions require at least 1
clock cycle to execute. Most require more.
• Wait states – empty clock cycles of
machine execution time (due to memory
access time being slower than speed of
clock).
Instruction Execution Cycle
• If using Memory operand (mov ax, 0A69Bh)
– Calculate address of operand
– Place address of operand on address bus
– Wait for memory to get operand and pass it on
data bus
Instruction Cycle
•
•
•
•
•
Fetch
Decode
Fetch memory operands
Execute
Store output operand
Pipelining Versus Non-Pipelining
• In non-pipelined systems, for k execution
states, n instructions require (n*k) cycles
to process.
• Using a pipelined system with k execution
states, n instructions require (k + (n-1))
cycles to complete.
Pipeline for 8086 (2-stage pipelining)
2-stage Pipelining
• Bus Interface Unit: accesses memory
and provides I/O
• Execution Unit: executes the
microcode instructions.
IA-32 Processor Pipelinig
(6-stage Pipelining)
• Bus Interface Unit: accesses memory and provides
I/O
• Code Prefetch Unit: receives instructions from the
BIU and inserts them into a holding area (instruction
queue)
• Instruction Decode Unit: decodes machine
instructions from the prefetch queue and translates
them into microcode.
• Execution Unit: executes the microcode instructions.
• Segment Unit: translates logical addresses into
linear addresses and performs protection checks
• Paging Unit: translates linear addresses into
physical addresses, performs page protection
checks and keeps a list of recently accessed pages
Superscalar Architecture
• Processors that allow two or more
execution pipelines (two or more
instructions can be in the execution stages
at the same time).
Reading from memory
• Typically the CPU clock is running much
faster than memory access time.
• Cache
– 1st Level – on chip
– 2nd Level – separate high speed RAM