Transcript PPRPCMOSSensorsArmagh2008_v3

CMOS Sensors
WP1-3
PPRP meeting
29 Oct 2008, Armagh
CMOS Technology
• CMOS = Complimentary Metal
Oxide Semiconductor
– Efficient way to build electronics
out of NMOS and PMOS
transistors
• Technology appeared in 70’s
– Driven by consumer electronics
market
– Used in PP for
electronics/computing
• PP Holy Grail: integrated
sensor and readout electronics
• Difference in requirements
– Industry: digital; visible light
imaging
– PP: analogue and digital at the
same time; detection of ionizing
particles
MAPS: Monolithic Active Pixel Sensors
• Signal detected in thin epi-layer,
< 20 mm
– Localized, excellent precision 1 mm
– Small signal, collection by diffusion
• Low noise
– Small capacitance
• Amplification in pixel allows to
preserve good Signal-to-Noise
• Limited choice as only NMOS
transistors are allowed
– PMOS transistors compete for charge
• Several PP groups follow the
approach of using existing
processes
– MIMOSA sensors, ….
Future Trends
• Affordable thin, low power and precise sensors
will revolutionize Particle Physics
• World-wide interest but only few groups have
design capability and access to this technology
– Fermilab, KEK, Strasbourg, INFN, LBL, RAL
– Expensive with complicated IP management
• Trend is to put more functionality inside pixels
– Started to be addressed in the last years (ex. deep nwell MAPS by INFN, vertical wafer integration by
Fermilab)
• UK is leading in two directions
– INMAPS: allows full CMOS inside pixel
– ISIS: allows raw charge storage
INMAPS
• Standard MAPS does not
allow CMOS
– Parasitic collection of charge
by other n-wells
• Shield n-wells with deep
p+ implant
– Ion beam of MeV energy
which stops at certain depth
• Full CMOS capability
– Increased complexity
– Reduced power
consumption
• RAL/CALICE pioneered
this process for PP
– Huge potential, a lot of
interest from outside of PP
ISIS: In Situ Storage
• Another way to enhance CMOS functionality
• Storage of raw charge
– Excellent noise immunity
– Reduced power consumption
• Implemented as n+ buried channel (as in CCD) and deep p+
implant
• Pioneered by LCFI for PP
– Only group with access to this technology
4T Structures
• 4T (four transistors)
structures allows efficient
charge capture and
amplification
– Now standard process
offered by foundries
– Offers better noise immunity
– Need studies for small
signal transfers from larger
capacitor
SPIDER Programme
• Based on three processes, INMAPS, ISIS and 4T which are
unique in PP
• Buried channel (ISIS)
– Have prove of concept: ISIS1
– Produced buried channel in CMOS technology: ISIS2
• Deep p+ (INMAPS)
– TPAC: first device to use INMAPS
– Cherwell: distributed architecture
• 4T process
– For Cherwell: first attempt to use 4T for scientific application
• Several years ahead of other groups
– Deep p+ planned by other groups but no practical implementation so far
– Strong interest in INMAPS multi-project runs
ISIS3
• ISIS2 produced by LCFI in
2008
– Test bed device with many
variants
– Used to optimize ISIS3
• ISIS3
– Refining the process
– Putting in more functionality
– Reducing pixel size (currently
10x80 mm2 )
Current load
80 μm
10 μm
Source follower
Pad
ISIS2 Pixel Geometry
TPAC2
• Large scale sensor
– Uses INMAPS
– Architecture inspired by
TPAC1 chip
• Designed for system
applications
– DCAL tests
TPAC1
Cherwell
(CDS circuit)
COL
• Distributed functionality with
no dead areas
CS
CR
BIAS
+ ∑
VTH
TRIM
– Enabled by INMAPS
– Rolling shutter readout
MEMORY [0]
Control logic
MEMORY [1]
MEMORY [2]
MEMORY [3]
MEMORY [4]
MEMORY [5]
MEMORY [6]
– Better noise immunity
COL
COL
• Cherwell will explore 4T
architecture for particle
detection for the first time
COL
WrEn MEMORY [7]
RESET
1x
SRAM
SELECT
Pixel
Boundary
50 um pixel
boundary
4
T
4
T
4
T
WP1: Sensor Design
• Design team based at RAL
Sensor Specification
Preliminary Design Review
• Design Specification
• Design reviews
– Oversees progress
– External Experts
• Submissions
• Handling of IP issues
Intermediate Design Review
Final Design Review
Sign-Off
Chip Submission
WP2: Sensor Modelling
• Signal collection
– ISIS: charge collection through
opening in deep p+
– TPAC/Cherwell: collection
efficiency
• Signal transfer
– 4T: transfer of small signal from
a large capacitance load
– ISIS: charge transfer in buried
channel
Charge collection in TPAC
Charge collection in ISIS
WP3: Sensor Characterization
• Share facilities and expertise between
institutions
Signal/Noise measurements
(Oxford,Imperial, Bristol)
Source Tests
Initial tests
(RAL)
(RAL)
Sensor
Evaluation
Laser Tests
Test Beams
(RAL)
(Bristol)
Irradiation
Cosmics
(Bristol)
(Birmingham)
WP3: Sensor Characterization
• Signal and Noise
– Radioactive sources 55Fe,
90Sr
– Performance integrated
over pixels
TPAC1
55Fe
signal
• Laser and source
mapping
– 1064 and 660 nm lasers
– Strong source to exercise
individual pixels
– Charge collection
– Threshold trimming
(TPAC)
ISIS1 Laser Map
Irradiation and Test Beams
• Irradiations will determine
sensor longevity in
experiments
– Surface damage
– Bulk damage
– Necessary to validate new
processes for wider
applications
MAPS before/after irradiation
• Two test beams, in 2010
and 2011
– Essential to measure
coordinate resolution and
efficiency
ISIS1 test beam
Knowledge Exchange
• Several pixel technologies were driven by PP
• CMOS technology was not driven by Particle
Physics but this may change
– INMAPS and ISIS modifications to standard CMOS
introduce very attractive features for other applications
– STFC and UK have leading positions
• ISIS: fast X-ray imaging
– Fast framing CCD imagers based on ISIS principle are
commercially produced
• Deep p+ (INMAPS) can be used for any fast and
specialized industrial imaging
Sensor Summary
• Pixel sensors with complex integrated
functionality is the future
• SPIDER will address this by R&D in three
directions: ISIS, INMAPS and 4T
• Sensor programme is based on
– ISIS3, TPAC, Cherwell
– Integrated approach to design, modelling and
testing
• Looking for applications outside of PP