Transcript Document

CMPUT329 - Fall 2003
TopicF: Static and Dynamic
Memories
José Nelson Amaral
CMPUT 329 - Computer
Organization and Architecture II
1
Reading Assignment
Chapter 10 of Wakerly
Sections 10.1, 10.2, 10.3, 10.4
CMPUT 329 - Computer
Organization and Architecture II
2
ALUOp
PcWrite
PcWriteCond
PCSource
IorD
ALUSelA
MemRead Control TargetWrite
MemWrite
Unit RegWrite
IRWrite
MemtoReg
ALUSelB
RegDst
Target
4
26
32
PC
0M
u
1x
Read
address
Memory
Write
address
MemData
Write
data
Instruction
[31-26]
Instruction
[25-0]
Instruction
register
I[25-21]
I[20-16]
0M
u
1x
[15-11]
0M
u
1x
I[15-0]
0M
1u
x
2
Conc/ 32
Shift
left 2
Read
register 1 Read
data 1
Read
register 2
Write
Read
register data
2
Write
data Registers
0M
u
1x
4
32
16 Sign
ext.
Shift
left 2
0
1M
u
2x
3
Zero
ALU
result
ALU
ALU
control
ALUOp
PcWrite
PcWriteCond
PCSource
IorD
ALUSelA
MemRead Control TargetWrite
MemWrite
Unit RegWrite
IRWrite
MemtoReg
ALUSelB
RegDst
Target
4
26
32
PC
0M
u
1x
Read
address
Memory
Write
address
MemData
Write
data
Instruction
[31-26]
Instruction
[25-0]
Instruction
register
I[25-21]
I[20-16]
0M
u
1x
[15-11]
0M
u
1x
I[15-0]
0M
1u
x
2
Conc/ 32
Shift
left 2
Read
register 1 Read
data 1
Read
register 2
Write
Read
register data
2
Write
data Registers
0M
u
1x
4
32
16 Sign
ext.
Shift
left 2
0
1M
u
2x
3
Zero
ALU
result
ALU
ALU
control
EPROMs
(Erasable Programmable Read Only Memories)
8K  8
16K  8
32K  8
64K  8
2764
27128
27256
27512
A0
A0
A1
A1
•
•
•
A12 A14
CS
OE
D0
O0
D1
O1
•
•
•
O7 D7
A0
A0
A1
A1
•
•
•
A13 A14
CS
OE
D0
O0
D1
O1
•
•
•
O7 D7
A0
A0
A1
A1
•
•
•
A14 A14
CS
OE
D0
O0
D1
O1
•
•
•
O7 D7
A0
A0
A1
A1
•
•
•
A15 A14
CS
OE
D0
O0
D1
O1
•
•
•
O7 D7
A0-A15: Address Bus
D0-D7: Data Bus
CS: Chip Select
OE: Output Enable
CMPUT 329 - Computer
Organization and Architecture II
5
Address Decoding on a
Microprocessor System
microprocessor
A0
A1
•
•
•
A19
D0
D1 •
•
•
27256
A0
A0
A1
A1
•
•
•
D0
O0
A14 A14
D1
O1
•
•
•
O7 D7
CS
OE
74x139
1G
1A
1B
1Y0
1Y1
1Y2
1Y3
D7
READ
WRITE
CMPUT 329 - Computer
Organization and Architecture II
6
The 74x139 Decoder
1G_L
74x139
1
1G
1Y0
1Y1
1A
13 1B
1Y2
1Y3
2
15
14
2G
2A
13 2B
1Y0_L
4
1Y1_L
5
6
7
12
2Y0
11
2Y1
2Y2 10
2Y3 9
1Y2_L
1A
1B
CMPUT 329 - Computer
Organization and Architecture II
1Y3_L
7
The 74x139 Decoder
1G_L
Inputs
Outputs
G_L A B Y0_L Y1_L Y2_L Y3_L
1 X X
0
0 0
0
0 1
0
1 0
0
1 1
1Y0_L
1Y1_L
1Y2_L
1A
1B
CMPUT 329 - Computer
Organization and Architecture II
1Y3_L
8
The 74x139 Decoder
1G_L
Inputs
Outputs
G_L A B Y0_L Y1_L Y2_L Y3_L
1 X X
0 0 0
0 0 1
0 1 0
0 1 1
1Y1_L
1Y2_L
1A
1
1Y0_L
1B
1Y3_L
0
CMPUT 329 - Computer
Organization and Architecture II
9
The 74x139 Decoder
1G_L
Inputs
Outputs
G_L A B Y0_L Y1_L Y2_L Y3_L
1
X X
1
1
1
1
0
0 0
0
0 1
0
1 0
0
1 1
1Y1_L
1Y2_L
1A
1
1Y0_L
1B
1Y3_L
0
CMPUT 329 - Computer
Organization and Architecture II
10
The 74x139 Decoder
1G_L
Inputs
Outputs
G_L A B Y0_L Y1_L Y2_L Y3_L
1 X X
1
1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1Y1_L
1Y2_L
1A
1
1Y0_L
1B
1Y3_L
0
CMPUT 329 - Computer
Organization and Architecture II
11
The 74x139 Decoder
1G_L
Inputs
Outputs
G_L A B Y0_L Y1_L Y2_L Y3_L
1 X X
1
1
1
1
0 0 0
0 0 1
0 1 0
0 1 1
1Y1_L
1Y2_L
1A
1
1Y0_L
1B
1Y3_L
0
CMPUT 329 - Computer
Organization and Architecture II
12
The 74x139 Decoder
1G_L
Inputs
Outputs
G_L A B Y0_L Y1_L Y2_L Y3_L
1
X X
1
1
1
1
0
0 0
0
1
1
1
0
0 1
0
1 0
0
1 1
1Y1_L
1Y2_L
1A
1
1Y0_L
1B
1Y3_L
0
CMPUT 329 - Computer
Organization and Architecture II
13
The 74x139 Decoder
1G_L
Inputs
Outputs
G_L A B Y0_L Y1_L Y2_L Y3_L
1 X X
1
1
1
1
0 0 0
0
1
1
1
0 0 1
1
0
1
1
0 1 0
1
1
0
1
0 1 1
1
1
1
0
1Y0_L
1Y1_L
1Y2_L
1A
1B
CMPUT 329 - Computer
Organization and Architecture II
1Y3_L
14
The 74x139 Decoder
Inputs
Outputs
1G 1A 1B 1Y0 1Y1 1Y2 1Y3
1 X X
1
1
1
1
0 0 0
0
1
1
1
0 0 1
1
0
1
1
0 1 0
1
1
0
1
0 1 1
1
1
1
0
74x139
1
1G
2
1A
13 1B
Inputs
Outputs
2G 2A 2B 2Y0 2Y1 2Y2 2Y3
1 X X
1
1
1
1
0 0 0
0
1
1
1
0 0 1
1
0
1
1
0 1 0
1
1
0
1
0 1 1
1
1
1
0
CMPUT 329 - Computer
Organization and Architecture II
15
14
2G
2A
13 2B
1Y0
1Y1
1Y2
1Y3
4
5
6
7
12
2Y0
11
2Y1
2Y2 10
2Y3 9
15
Address Decoding
We want to design a microprocessor-based system
with 128 Kbytes of EPROM using the 27256 EPROM
chips that have an organization of 32K  8 bits.
This particular microprocessor has a data bus that is
8-bit wide and an address bus that is 20-bits wide.
The EPROM is to be mapped to the highest addresses
of the memory address space.
CMPUT 329 - Computer
Organization and Architecture II
16
Address Decoding
A memory address in this system has the following
format:
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
32 Kbytes = 32  1024 = 25  210 = 215 bytes
Thus we need 15 address lines to address 32 Kbytes.
Therefore, the 32K highest addresses in this memory
system have the following addresses.
19 18 17 16 15 14 13 12 11 10
1
1
1
1
9
8
7
6
5
4
3
2
1
0
1
CMPUT 329 - Computer
Organization and Architecture II
17
Address Decoding
The 64K highest addresses are the following addresses.
19 18 17 16 15 14 13 12 11 10
1
1
1
9
8
7
6
5
4
3
2
1
0
5
4
3
2
1
0
1
And the 128K highest addresses are:
19 18 17 16 15 14 13 12 11 10
1
1
9
8
7
6
1
CMPUT 329 - Computer
Organization and Architecture II
18
Address Decoding
Thus to verify if a memory access is to the EPROM
region, we can just verify if the address lines A19,
A18, and A17 are simultaneously 1:
19 18 17 16 15 14 13 12 11 10
1
1
9
8
7
6
5
4
3
2
1
0
1
A19
A18
HIMEN_L
A17
CMPUT 329 - Computer
Organization and Architecture II
19
Address Decoding
To create a space of 128 Kbytes of EPROM with chips
that have 32 Kbytes capacity, we will need four memory
chips.
How can we use the address lines to identify which
memory chip is been accessed each time?
CMPUT 329 - Computer
Organization and Architecture II
20
Address Decoding
The memory chip placed at the higher portion of
the address space contains the memory addresses
starting at:
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
F8000
And ending at:
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
FFFFF
CMPUT 329 - Computer
Organization and Architecture II
21
Address Decoding
Bank
3
Bank
2
Bank
1
Bank
0
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CMPUT 329 - Computer
Organization and Architecture II
F8000
FFFFF
F0000
F7FFF
E8000
EFFFF
E0000
E7FFF
22
Address Decoding
Bank
3
Bank
2
Bank
1
Bank
0
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 1 1 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 1 1 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 1 1 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 1 1 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 1 0 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 1 0 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
1 1 1 0 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1 1 1 0 0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CMPUT 329 - Computer
Organization and Architecture II
F8000
FFFFF
F0000
F7FFF
E8000
EFFFF
E0000
E7FFF
23
Address Decoding on a
Microprocessor System
microprocessor
A0
A0
A1
A1
•
•
•
A19
A19
27256
A0
A0
A1
A1
•
•
•
D0
O0
A14 A14
D1
O1
•
•
•
O7
CS
D7
27256
A0
A0
A1
A1
•
•
•
D0
O0
A14 A14
D1
O1
•
•
•
O7
CS
D7
OE
27256
A0
A0
A1
A1
•
•
•
D0
O0
A14 A14
D1
O1
•
•
•
O7
CS
D7
OE
OE
27256
A0
A0
A1
A1
•
•
•
D0
O0
A14 A14
D1
O1
•
•
•
O7
CS
D7
OE
D0
D0
D1
D1 •
•
•
D7
D7
READ
WRITE
A19
A18
A17
A15
A16
HIMEN_L
74x139
1G
1A
1B
SE0000_L
1Y0
SE8000_L
1Y1
SF0000_L
1Y2
1Y3 SF8000_L
24
Types of Memories
Read/Write Memory (RWM): we can store and retrieve data.
Random Access Memory (RAM): the time required to read or
write a bit of memory is independent of the bit’s location.
Static Random Access Memory (SRAM): once a word is written
to a location, it remains stored as long as power is applied
to the chip, unless the location is written again.
Dynamic Random Access Memory (DRAM): the data stored at
each location must be refreshed periodically by reading it and
then writing it back again, or else it disappears.
CMPUT 329 - Computer
Organization and Architecture II
25
Random Access Memories
(RAMs)
A Random-Access Memory (RAM) is so called to contrast with
its predecessor, the Serial-Access Memory. In a serial access
memory, memory positions become available for reading on
a sequential fashion. Therefore to read an specific memory
position, the reader must wait a variable time delay for the
memory position to became available.
In principle, in a RAM, all positions of the memory can
be read on a random fashion with approximately the
same delay for all positions.
However, modern RAMs allow burst accesses that favor
sequential accesses (complete them in less time).
CMPUT 329 - Computer
Organization and Architecture II
26
Static-RAM Control Inputs
The outputs of memory chips are often connected to
a three-state bus, a bus that can be driven by many
devices. Therefore each memory chip should drive the
bus only when commanded to do so by the control logic.
The following control inputs are typically used to control
a Static-RAM.
Output Enable (OE): Enable the output into the data lines
Chip Select (CS): Used in connection with OE to simplify
the design of a multiple chip system.
Write Enable (WE): When asserted, the data inputs are
written to the selected memory location.
CMPUT 329 - Computer
Organization and Architecture II
27
A 2nb SRAM
Address
inputs
A0
A1
2n  b SRAM
An-1
Data
inputs
control
inputs
DIN0
DIN1
DOUT0
DOUT1
DINb-1
DOUTb-1
Data
outputs
CS
OE
WE
CMPUT 329 - Computer
Organization and Architecture II
28
SRAMs
(Static Random Access Memories)
HM6264
HM62256
HM628128
HM628512
2764
2764
2764
2764
A0
A0
A1
A1
•
•
•
A12
A12
WE
CS1
CS2
OE
D0
IO0
D1
IO1
•
•
•
D7
IO7
A0
A0
A1
A1
•
•
•
A14
A14
WE
CS
OE
D0
IO0
D1
IO1
•
•
•
D7
IO7
A0
A0
A1
A1
•
•
•
A16
A16
WE
CS1
CS2
OE
CMPUT 329 - Computer
Organization and Architecture II
D0
IO0
D1
IO1
•
•
•
D7
IO7
A0
A0
A1
A1
•
•
•
A18
A18
WE
CS
OE
D0
IO0
D1
IO1
•
•
•
D7
IO7
29
Accesses to SRAM
Read An address is placed on the address inputs while
CS and OE are asserted. The latch outputs for the
selected memory locations are delivered to DOUT.
Write An address is placed on the address inputs and
a data word is placed on DIN; then CS and WE are
asserted. The latches in the selected memory
location open, and the input word is stored.
CMPUT 329 - Computer
Organization and Architecture II
30
DIN3
0
3-to-8
decoder
1
2
0 A2
1 A1
1 A0
2
3
1
0
4
5
6
7
WE_L
CS_L
DIN2
DIN1
DIN0
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
WR_L
IOE_L
OE_L
DOUT3
DOUT2
DOUT1
DOUT0
DIN3
0
3-to-8
decoder
1
2
0 A2
1 A1
1 A0
2
3
1
0
4
5
6
7
WE_L
CS_L
DIN3
DIN3
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
WR_L
IOE_L
OE_L
DOUT3
DOUT3
DOUT3
DOUT3
DIN3
0
3-to-8
decoder
1
2
0 A2
1 A1
1 A0
2
3
1
0
4
5
6
7
WE_L
CS_L
DIN3
DIN3
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
WR_L
IOE_L
OE_L
DOUT3
DOUT3
DOUT3
DOUT3
DIN3
0
3-to-8
decoder
1
2
0 A2
1 A1
1 A0
2
3
1
0
4
5
6
7
WE_L
CS_L
DIN3
DIN3
DIN3
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
WR_L
IOE_L
OE_L
DOUT3
DOUT3
DOUT3
DOUT3
SRAM with Bi-directional
Data Bus
microprocessor
IN OUT
SEL
WR
WE_L
CS_L
IN OUT
SEL
WR
IN OUT
SEL
WR
IN OUT
SEL
WR
WR_L
IOE_L
OE_L
DIO3
DIO2
CMPUT 329 - Computer
Organization and Architecture II
DIO1
DIO0
35
Internal Address Decoding
The SRAM shown in the previous slides had 3 address
lines and stored 8 words, requiring a 3-to-8 internal
decoder.
Such a decoder requires eight AND gates, with
three inputs each, and three inversors.
Consider the HM628512 SRAM that has 19 address
lines and stores 512K words. What size internal
decoder this chip requires?
A 19-to-512K decoder with 524288 AND gates, each
with 19 inputs?
CMPUT 329 - Computer
Organization and Architecture II
36
Internal Address Decoding
To avoid such a complexity in the decoding logic,
all memories (EPROMs, SRAMs, and DRAMs) use
two-dimensional decoding which reduces the
decoder size to approximately the square root
of the number of addresses.
The memory cells are organized in a two-dimensional
array. Some address lines are used to select a row
and the others are used to select a column. The
cell selected by the whole address is at the intersection
of the row and the column.
CMPUT 329 - Computer
Organization and Architecture II
37
Static-RAM Read Timing
tAA (access time for address): how long it takes to get stable
output after a change in address.
tACS (access time for chip select): how long it takes to get stable
output after CS is asserted.
tOE (output enable time): how long it takes for the three-state
output buffers to leave the high-impedance state when
OE and CS are both asserted.
tOZ (output-disable time): how long it takes for the three-state
output buffers to enter high-impedance state after
OE or CS are negated.
tOH (output-hold time): how long the output data remains
valid after a change
to329
the
address inputs.
CMPUT
- Computer
Organization and Architecture II
38
Static-RAM Read Timing
stable
ADDR
stable
stable
 tAA
Max(tAA, tACS)
CS_L
tOH
tACS
OE_L
tAA
DOUT
tOZ
valid
tOE
tOZ
valid
WE_LCMPUT
= HIGH329 - Computer
Organization and Architecture II
tOE
valid
39
Static-RAM Write Timing
tAS (address setup time before write): all address inputs must be
stable at this time before both CS and WE are asserted.
tAH(address hold time after write): all address inputs must be held
stable until this time after CS or WE is negated.
tCSW (chip-select setup before end of write): CS must be asserted
at least this long before the end of the write cycle.
tWP (write pulse width): WE must be asserted at least this long
to reliably latch data into the selected cell.
tDS (data setup time before end of write): All of the data inputs
must be stable at this time before the write cycle ends.
tDH (data hold time after the end of write): All data inputs must
be held stable until
this329time
after the write cycle ends.
CMPUT
- Computer
Organization and Architecture II
40
Dynamic Memory Cell
An SRAM cell has a bi-stable latch that requires from
four to six transistors to be built.
To deliver the higher memory density required for
computer systems, a single transistor memory cell
was developed.
bit line
word line
1-bit DRAM cell
CMPUT 329 - Computer
Organization and Architecture II
41
Writing 1 in a Dynamic
Memories
bit line
word line
1-bit DRAM cell
To store a 1 in this cell, a HIGH voltage is placed on
the bit line, causing the capacitor to charge through
the on transistor.
CMPUT 329 - Computer
Organization and Architecture II
42
Writing 0 in a Dynamic
Memories
bit line
word line
1-bit DRAM cell
To store a 0 in this cell, a LOW voltage is placed on
the bit line, causing the capacitor to discharge through
the on transistor.
CMPUT 329 - Computer
Organization and Architecture II
43
Destructive Reads
bit line
word line
1-bit DRAM cell
To read the DRAM cell, the bit line is precharged to
a voltage halfway between HIGH and LOW, and
then the word line is set HIGH.
Depending on the charge in the capacitor, the precharged
bit line is pulled slightly higher or lower.
A sense amplifier detects this small change and
recovers a 1 CMPUT
or a 0.329 - Computer
Organization and Architecture II
44
Recovering from
Destructive Reads
bit line
word line
1-bit DRAM cell
The read operation discharges the capacitor.
Therefore a read operation in a dynamic memory must
be immediately followed by a write operation of the same
value read to restore the capacitor charges.
CMPUT 329 - Computer
Organization and Architecture II
45
Forgetful Memories
bit line
word line
1-bit DRAM cell
The problem with this cell is that it is not bi-stable:
only the state 0 can be kept indefinitely, when the
cell is in state 1, the charge stored in the capacitor
slowly dissipates and the data is lost.
CMPUT 329 - Computer
Organization and Architecture II
46
Refreshing the Memory
1 written
Vcap
refreshes
VCC
HIGH
LOW
0V
time
0 stored
The solution is to periodically refresh the memory
cells by reading and writing back each one of them.
CMPUT 329 - Computer
Organization and Architecture II
47
Refreshing Frequency
Each dynamic RAM cell must be refreshed at about
every 4 miliseconds.
Some commercial DRAMs contain 256 megabits.
If we would refresh each cell every 4 miliseconds
we would have to perform a refresh operation every:
4ms
4 103

 0.015ns  15 p sec
6
256Mcells 256 10
There would be no time for regular memory accesses!!
How do we solve this problem?
CMPUT 329 - Computer
Organization and Architecture II
48
Refreshing Memory
The DRAMs are organized in two dimensional arrays,
and a single refreshing operation can refresh an entire
row at a time.
Newer DRAMs have 4096 rows, but only need to be
refreshed every 64 miliseconds. Therefore they require
one refresh operation about every 15.6 second.
A refresh operation typically takes 100 nanoseconds.
Therefore the memory is available for regular accesses
more than 99% of the time.
CMPUT 329 - Computer
Organization and Architecture II
49
Internal Structure of a
64K  1 DRAM
256  256
array
Row
decoder
row
address
A0-A7
RAS_L
CAS_L
WE_L
column
address
control
latch, mux, and
dmux control
Column latches,
multiplexers,
and demultiplexers
DOUT
CMPUT 329 - Computer
Organization and Architecture II
DIN
50
Step 1: Apply row address
Step 2: RAS go from high
to low and remain low
2
8
Step 3: Apply column address
5
Step 4: WE must be high
Step 5: CAS goes from high
to low and remain low
3
1
Step 6: OE goes low
4
Step 7: Data appears
6
Step 8: RAS and CAS
return to high
7
Read Cycle on an Asynchronous DRAM
Write Cycle on an Asynchronous DRAM
Improved DRAMs
Central Idea: Each read to a DRAM actually
reads a complete row of bits or word line from
the DRAM core into an array of sense amps.
A traditional asynchronous DRAM interface
then selects a small number of these bits to be
delivered to the cache/microprocessor.
All the other bits already extracted from the DRAM
cells into the sense amps are wasted.
CMPUT 329 - Computer
Organization and Architecture II
53
Fast Page Mode DRAMs
In a DRAM with Fast Page Mode, a page is defined as
all memory addresses that have the same row address.
To read in fast page mode, all the steps from 1 to 7 of
a standard read cycle are performed.
Then OE and CAS are switched high, but RAS remains
low.
Then the steps 3 to 7 (providing a new column address,
asserting CAS and OE) are performed for each new
memory location to be read.
CMPUT 329 - Computer
Organization and Architecture II
54
A Fast Page Mode Read Cycle on an Asynchronous DRAM
Enhanced Data Output
RAMs (EDO-RAM)
The process to read multiple locations in an EDO-RAM
is very similar to the Fast Page Mode.
The difference is that the output drivers are not disabled
when CAS goes high.
This distintion allows the data from the current read cycle
to be present at the outputs while the next cycle
begins.
As a result, faster read cycle times are allowed.
CMPUT 329 - Computer
Organization and Architecture II
56
An Enhanced Data Output Read Cycle on an Asynchronous DRAM
Synchronous DRAMs
(SDRAM)
A Synchronous DRAM (SDRAM) has a clock input. It operates
in a similar fashion as the fast page mode and EDO DRAM.
However the consecutive data is output synchronously on the
falling/rising edge of the clock, instead of on command by
CAS.
How many data elements will be output (the length of
the burst) is programmable up to the maximum size of
the row.
The clock in an SDRAM typically runs one
order of magnitude faster than the access time for
individual accesses.
CMPUT 329 - Computer
Organization and Architecture II
58
SDRAM Burst Read Cycle
CMPUT 329 - Computer
Organization and Architecture II
59
DDR SDRAM
A Double Data Rate (DDR) SDRAM is an SDRAM
that allows data transfers both on the rising and
falling edge of the clock.
Thus the effective data transfer rate of a DDR
SDRAM is two times the data transfer rate of
a standard SDRAM with the same clock frequency.
CMPUT 329 - Computer
Organization and Architecture II
60
The Rambus DRAM
(RDRAM)
Multiple memory arrays (banks)
Rambus DRAMs are synchronous and
transfer data on both edges of the clock.
CMPUT 329 - Computer
Organization and Architecture II
61
SDRAM Memory Systems
Complex circuits for
RAS/CAS/OE.
Each DIMM is connected
in parallel with the memory
controller.
(DIMM = Dual In-line
Memory Module)
Often requires buffering.
Needs the whole clock
cycle to establish valid data.
Making the bus wider is
mechanically complicated.
CMPUT 329 - Computer
Organization and Architecture II
62
RDRAM Memory Systems
CMPUT 329 - Computer
Organization and Architecture II
63
Internal RDRAM
Organization
CMPUT 329 - Computer
Organization and Architecture II
64
SDRAM Protocol
Write
Read
Notice the different delays between RAS and the first data
in the data bus for read and write operations. This creates
bubbles when transiting from write to read.
CMPUT 329 - Computer
Organization and Architecture II
65
RDRAM Protocol
CMPUT 329 - Computer
Organization and Architecture II
66
Bank Conflicts
If two consecutive memory accesses are accessing
the same memory bank, there will be a delay, or
a bubble, in the response.
This delay happens because a memory device
needs time to “recover” after it completes a
memory access.
Thus the more banks a memory system has,
the less likely it will be to have delays caused
by memory bank conflicts.
CMPUT 329 - Computer
Organization and Architecture II
67
SDRAM Bank Conflicts
CMPUT 329 - Computer
Organization and Architecture II
68
RDRAM Banks  SDRAM
Banks
CMPUT 329 - Computer
Organization and Architecture II
69
Dual In-line Memory
Module (DIMM)
CMPUT 329 - Computer
Organization and Architecture II
70
Rambus In-line Memory
Module (RIMM)
CMPUT 329 - Computer
Organization and Architecture II
71
A picture of RIMMs
CMPUT 329 - Computer
Organization and Architecture II
72
Further Reading
To learn more about the differences between
SDRAM systems and Rambus DRAM systems
for personal computers, visit these websites:
http://www.hardwarecentral.com/hardwarecentral/reviews/1787/1/
http://www.pcguide.com/ref/ram/tech_SDRAM.htm
Crisp, Richard, “Direct Rambus Technology: The New Main
Memory Standard,” IEEE Micro, 17(6): 18-28, Nov/Dec, 1997.
CMPUT 329 - Computer
Organization and Architecture II
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