Transcript Slides - Computer Engineering Research Center

Sub-lithographic
Semiconductor Computing
Systems
André DeHon
[email protected]
In collaboration with
Helia Naeimi, Michael Wilson, Charles Lieber,
Patrick Lincoln, and John Savage
UT Oct. 2004 -- DeHon
Approaching the Bottom
• In 1959, Feynman pointed out we had
– “plenty of room at the bottom”
• Suggested:
– wires ~ 10-100 atoms diameter
– circuits ~ few thousands angstroms
~ few hundred nm
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Approaching the Bottom
• Today we have 90nm Si processes
– bottom is not so far away
• Si Atom
– 0.5nm lattice spacing
– 90nm ~ 180 atoms diameter wire
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Exciting Advances in Science
• Beginning to be able to manipulate
things at the “bottom” -- atomic scale
engineering
– designer/synthetic molecules
– carbon nanotubes
– silicon nanowires
– self-assembled mono layers
– designer DNA
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Question
• Can we build interesting computing
systems without lithographic patterning?
• Primary interest:
below lithographic limits
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Why do we care?
• Lithographic limitations
– Already stressing PSM
– …xrays, electron projection…
$50,000,000
Exposure tool price
• Lithographic costs
$40,000,000
Source: Kahng/ITRS2001
$30,000,000
$20,000,000
$10,000,000
$0
1980
1985
1990
1995
Year
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2000
2005
Today’s Talk
Bottom up tour: from Si atoms to Computing
• Nanowire
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–
–
–
•
•
•
•
growth
devices
assembly
differentiation
coding
Nanoscale memories from nanowires
Logic: nanoPLAs
Interconnected nanoPLAs
Analysis
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SiNW
Growth
• Atomic structure
determines
feature size
• Self-same crystal
structure
constrains growth
• Catalyst
defines/constrains
structure
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SiNW Growth
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SiNW Growth
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Building Blocks
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Semiconducting Nanowires
• Few nm’s in diameter (e.g. 3nm)
– Diameter controlled by seed catalyst
• Can be microns long
• Control electrical properties via doping
– Materials in environment during growth
– Control thresholds for conduction
From:
Cui…Lieber
APL v78n15p2214
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Radial Modulation Doping
• Can also control doping profile radially
– To atomic precision
– Using time
Lauhon et. al.
Nature 420 p57
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Devices
Doped nanowires give:
Diode and FET Junctions
Cui…Lieber
Science 291 p851
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Huang…Lieber
Science 294 p1313
Langmuir-Blodgett (LB) transfer
• Can transfer tight-packed, aligned SiNWs
onto surface
– Maybe grow sacrificial outer radius, close pack,
and etch away to control spacing
Transfer aligned
NWs to patterned
substrate
Transfer second
layer at right
angle
+
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Whang, Nano Letters 2003 (to appear)
Homogeneous Crossbar
• Gives us homogeneous NW crossbar
– Undifferentiated wires
– All do the same thing
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Control NW Dopant
• Can define a dopant profile along
the length of a wire
– Control lengths by timed growth
– Change impurities present in the
environment as a function of time
Gudiksen et. al.
Nature 415 p617
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Björk et. al.
Nanoletters 2 p87
Control NW Dopant
• Can define a dopant profile along
the length of a wire
– Control lengths by timed growth
– Change impurities present in the
environment as a function of time
• Get a SiNW banded with
differentiated conduction/gate-able
regions
Gudskien et. al.
Nature 415 p617
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Björk et. al.
Nanoletters 2 p87
Enables: Differentiated Wires
• Can engineer wires
– Portions of wire always
conduct)
– Portions controllable
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Coded Wires
• By selectively making bit-regions on
wires either highly or lightly doped
– Can give the wire an address
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Unique Set of Codes
• If we can assemble a
set of wires with
unique codes
– We have an address
decoder
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Unique Set of Codes
• If we can assemble a
set of wires with
unique codes
– We have an address
decoder
• Apply a code
– k-hot code
• Unique code
selects a single
wire
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Statistical Coding
• Unique Code set achievable with
statistical assembly (random mixing)
• Consider:
– Large code space (106 codes)
– Large number of wires of each type (1012)
– Small array (10 wires) chosen at random
• Likelihood all 10 unique?
– Very high! (99.995%)
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DeHon et. al.
IEEE TNANO v2n3p165
Codespace: How Large?
• How large does code space really need
to be?
– Addressing N wires
– With code space 100N2
– Has over 99% probability of all wires being
unique
– For logarithmic decoder:
• Need a little over 2 bits of sparse code
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Switches / Memories
Molecular
Switches
Collier et. al.
Science 289 p1172
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Electrostatic
Switches
Ruekes et. al.
Science 289 p04
Common Switchpoint
Properties
• Fit in space of NW crossing
• Hysteretic I-V curves
• Set/reset with large differential voltage
across crosspoint
• Operate at lower voltage
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Memories
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Basis for Sublithographic
Memory
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Precharge all lines low
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Drive Column Read Address
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Pulls Single Column Line High
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On xpoint allow to pull Row lines
to be pulled high
Assume here:
only the two
points shown
are “on”.
i.e. column has
010010
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All Rows Disabled
Read output
not driven;
sees 0
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Select Read Row 1010
Read output
now pulled
high; sees 1
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Select Read Row 1100
Read output
not driven;
sees 0
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…on to Logic…
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Diode Logic
• Arise directly from
touching NW/NTs
• Passive logic
• Non-restoring
• Non-volatile
Programmable
crosspoints
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Use to build Programmable
OR-plane
• But..
– OR is not universal
– Diode logic is non-restoring  no gain, cannot
cascade
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PMOS-like
Restoring FET Logic
• Use FET
connections to
build restoring
gates
• Static load
– Like NMOS
(PMOS)
• Maybe precharge
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Ideal vs. Stochastic Restore
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Simple Nanowire-Based PLA
NOR-NOR = AND-OR PLA Logic
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Defect Tolerant
All components (PLA, routing, memory) interchangeable;
Have M-choose-N property
Allows local programming around faults
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Simple PLA Area
• 60 OR-term PLA
– Useable
• 131 raw row
wires
– Defects
– Misalign
• 171 raw
inverting wires
– Defects
– Statistical
population
• 60M sq. nm.
– (2 planes)
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90nm support lithography;
10nm nanowire pitch
Crosspoint Defects
• Crosspoint junctions may be
nonprogrammable
– E.g. HPs first 8x8 had 85%
programmable crosspoints
• Tolerate by matching
nanowire junction
programmability with pterm
needs
• Less than ~10% overhead
for crosspoint defect rates
up to 20%
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Naeimi/DeHon, FPT2004
Interconnected nanoPLAs
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Tile into Arrays
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Manhattan Routing
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Manhattan Routing
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Tile into Arrays
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Complete Substrate for
Computing
• Know NOR gates are
universal
• Selective inversion
• Interconnect structure for
arbitrary routing
Can compute any logic
function
• Can combine with
nanomemories
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Interconnected
nanoPLA Tile
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Analysis
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Ideal vs. Stochastic Restore
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Various Area Models
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Technology:
Lithographic Support
+ Diode Pitch
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Area Mapped Logic
• Take standard CAD/Benchmark designs
– Toronto20 used for FPGA evaluation
• Map to PLAs
• Place and Route on arrays of various
configurations
• Pick Best mapping to minimize Area
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Mapped Logic Density (105/10/5)
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Cycle Delay:
105/10/5/Ideal Restore/Pc=0.95
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Power Density (per GHz)
• Vdd=1V
• Active Power
• Precharge
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Construction Review
•
•
•
•
•
•
Seeding control NW diameter
Timed growth controls doping profile along NW
LB flow to assemble into arrays
Timed etches to separate/expose features
Assemble on lithographic scaffolding
Stochastic construction of address coding allow
micronanoscale addressing
• Differentiate at nanoscale via post-fabrication
programming
• All compatible with conventional semiconductor
processing
– Key feature is decorated nanowires
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Summary
• Can engineer designer structures at atomic scale
• Must build regular structure
– Amenable to self-assembly
• Can differentiate
– Stochastically
– Post-fabrication programming
• Sufficient building blocks to define universal
computing systems without lithography
• Reach or exceed extreme DSM lithography
densities
– With modest lithographic support
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Additional Information
• <http://www.cs.caltech.edu/research/ic/>
• <http://www.cmliris.harvard.edu/>
UT Oct. 2004 -- DeHon