Transcript Lec2 Logic Gates

2010 R&E Computer System Education & Research
Lecture 2. Logic Gates
Prof. Taeweon Suh
Computer Science Education
Korea University
Logic Gates
• Logic gates perform logic functions such as NOT
(inversion), AND, OR, NAND, NOR, etc.
 Single-input logic gates
• NOT gate, buffer
 Two-input logic gates
• AND, OR, XOR, NAND, NOR, XNOR etc
 Multiple-input logic gates
• AND, OR, XOR, NAND, NOR, XNOR etc
2
Korea Univ
Single-Input Logic Gates
BUF
NOT
A
A
Y
Y=A
Y=A
A
0
1
Y
A
0
1
Y
1
0
3
Y
0
1
Korea Univ
Two-Input Logic Gates
AND
A
B
OR
A
B
Y
Y = AB
A
0
0
1
1
B
0
1
0
1
Y
Y=A+B
Y
0
0
0
1
A
0
0
1
1
4
B
0
1
0
1
Y
0
1
1
1
Korea Univ
More Two-Input Logic Gates
XOR
A
B
NAND
A
B
Y
Y=A+B
A
0
0
1
1
•
B
0
1
0
1
NOR
A
B
Y
Y = AB
Y
0
1
1
0
A
0
0
1
1
B
0
1
0
1
XNOR
Y
Y=A+B
Y
1
1
1
0
A
0
0
1
1
B
0
1
0
1
A
B
Y
Y=A+B
Y
1
0
0
0
A
0
0
1
1
B
0
1
0
1
Y
2 input XOR (Exclusive OR) is “true” if either A or B (not both) is true
5
Korea Univ
Multiple-Input Logic Gates
AND4
NOR3
A
B
C
A
B
C
D
Y
Y = ABCD
Y = A+B+C
A
0
0
0
0
1
1
1
1
•
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Y
Y
Note that N-input XOR is “true” if an odd number of inputs is true
6
Korea Univ
Logic Levels
• Logic levels define discrete voltages to represent
1 and 0
 For example, we could define:
• 0 to be 0 volts (ground)
• 1 to be 5 volts (VDD)
 But what if our gate produces, for example, 4.99
volts? Is that a 0 or a 1?
 What about 3.2 volts?
7
Korea Univ
Logic Levels
• Define a range of voltages to represent 1 and 0
• Define different ranges for outputs and inputs to
allow for noise in the system
 Noise is anything that degrades the signal
• For example, a gate (driver) could output a 5 volt signal but,
because of losses in the wire and other noise, the signal
could arrive at the receiver with a degraded value, for
example, 4.5 volts
Noise
Driver
Receiver
5V
4.5 V
8
Korea Univ
Logic Levels
Driver
Receiver
Output Characteristics
Logic High
Output Range
VO H
VDD
Input Characteristics
Logic High
Input Range
NMH
Forbidden
Zone
VO L
NML
Logic Low
Output Range
GND
VIH
VIL
Logic Low
Input Range
Noise Margin
NMH = VOH – VIH
NML = VIL – VOL
9
Korea Univ
BTW, How Logic Gates are Built?
• What we saw so far are just symbols, right?
• What are those symbols built from in the real world?
NOT
A
Y
Y=A
A
0
1
A
Y
A
B
A
0
1
Y
A
B
Y = AB
Y=A
Y
1
0
OR
AND
BUF
A
0
0
1
1
Y
0
1
B
0
1
0
1
Y
Y=A+B
Y
0
0
0
1
A
0
0
1
1
B
0
1
0
1
Y
0
1
1
1
Transistors!
10
Korea Univ
Transistor
• Transistor is a three-ported voltage-controlled
switch
 Two of the ports are connected depending on the voltage on
the third port
 For example, in the switch below the two terminals (d and s)
are connected (ON) only when the third terminal (g) is 1
• Hmmm, it is still a symbol! What is it really built from?
d
g=0
g=1
d
d
g
ON
OFF
s
s
s
11
Korea Univ
Silicon
• Transistors are built out of silicon, a
semiconductor
• Silicon is not a conductor
• Doped silicon is a conductor
wafer
– n-type (free negative charges, electrons)
– p-type (free positive charges, holes)
Free electron
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Si
Silicon Lattice
Free hole
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
-
+
n-Type
12
+
-
Si
Si
Si
p-Type
Korea Univ
Periodic Table of the Elements
13
Korea Univ
MOS Transistors
• Metal oxide silicon (MOS) transistors:
– Polysilicon (used to be Metal) gate
– Oxide (silicon dioxide) insulator
– Doped Silicon substrate and wells
source
gate
source
drain
gate
drain
Polysilicon
SiO2
n
p
n
p
p
n
substrate
gate
source
substrate
gate
drain
source
nMOS
drain
pMOS
14
Korea Univ
MOS Transistors
• The MOS sandwich acts as a capacitor (two conductors
with insulator between them)
• When voltage is applied to the gate, the opposite charge
is attracted to the semiconductor on the other side of
the insulator, which could form a channel of charge
source
gate
source
drain
gate
drain
Polysilicon
SiO2
n
p
n
p
p
n
substrate
gate
source
substrate
gate
drain
source
nMOS
drain
pMOS
15
Korea Univ
nMOS Transistor
Gate = 0 (OFF)
Gate = 1 (ON)
(no connection between source and drain)
(connection between source and drain)
source
drain
source
gate
gate
VDD
drain
GND
n
n
p
n
+++++++
------channel
p
substrate
GND
n
substrate
GND
16
Korea Univ
pMOS Transistor
Gate = 0 (ON)
Gate = 1 (OFF)
(connection between source and drain)
(no connection between source and drain)
source
gate
drain
Polysilicon
SiO2
p
p
n
substrate
gate
source
drain
17
Korea Univ
Transistor Function
d
nMOS
pMOS
g=0
g=1
d
d
OFF
g
ON
s
s
s
s
s
s
g
OFF
ON
d
d
18
d
Korea Univ
CMOS (Complementary MOS)
• CMOS is used to build the vast majority of all transistors
fabricated today
 nMOS transistors pass good 0’s, so connect source to GND
 pMOS transistors pass good 1’s, so connect source to VDD
pMOS
pull-up
network
inputs
output
nMOS
pull-down
network
19
Korea Univ
CMOS Layout
• Top view
• Cross-section
20
Korea Univ
Is this CMOS that CMOS in Computer?
• Non-volatile BIOS memory
(NVRAM) refers to a small
memory on PC motherboards
that is used to store BIOS
settings
 The NVRAM has a typical
capacity of 512 Bytes, which is
enough for all BIOS-settings
 It was traditionally called
CMOS RAM because it used a
low-power CMOS SRAM
powered by a small battery
 The term remains in wide use,
but it has grown into a
misnomer
 Non-volatile storage in
contemporary computers is
often in EEPROM or flash
memory
21
Korea Univ
NOT Gate
NOT
A
Layout (top view)
VDD
Y
A
Y=A
A
0
1
P1
Y
N1
Y
1
0
GND
A
P1
N1
Y
0
ON
OFF
1
1
OFF
ON
0
22
Korea Univ
NAND Gate
NAND
A
B
P2
Y
B
0
1
0
1
Y
1
1
1
0
P1
Y
Y = AB
A
0
0
1
1
Layout
A
N1
B
N2
A
B
P1
P2
N1
N2
Y
0
0
ON
ON
OFF
OFF
1
0
1
ON
OFF
OFF
ON
1
1
0
OFF
ON
ON
OFF
1
1
1
OFF
OFF
ON
ON
0
23
Korea Univ
3-Input NAND Gate
• How do you build a three-input NAND gate?
Y
A
B
C
24
Korea Univ
So, Let’s Make an Inverter Chip
Core 2 Duo
Your
Inverter
chip
25
Korea Univ
(Semiconductor) Technology
• IC (Integrated Circuit) combined dozens to hundreds of transistors
into a single chip
• VLSI (Very Large Scale Integration) is used to describe the
tremendous increase in the number of transistors in a chip
• (Semiconductor) Technology: How small can you make a transistor
 0.1 µm (100nm), 90nm, 65nm, 45nm, 32nm technologies
source
gate
source
drain
gate
drain
Polysilicon
SiO2
n
n
p
p
p
n
substrate
gate
source
substrate
gate
drain
source
nMOS
drain
pMOS
26
Korea Univ
Feature Size (Technology) Trend
27
Korea Univ
Intel Founders
• Robert Noyce (1927~1990)
 Nicknamed “Mayor of Silicon Valley”
 Cofounded Fairchild Semiconductor in
1957
 Cofounded Intel in 1968
 Co-invented the integrated circuit (IC)
• Gorden Moore (1929~)
 Cofounded Intel in 1968 with Robert
Noyce.
 Moore’s Law: the number of transistors
on a computer chip doubles every year
(observed in 1965)
 Since 1975, transistor counts have
doubled every two years
28
Korea Univ
Moore’s Law
• Transistor count will be doubled every 18 months
1.7
billions
Montecito
42millions
2,250
Exponential
growth
29
Korea Univ
x86 History (as of 2008)
30
Korea Univ
x86?
• What is x86?
 Generic term referring to processors from Intel, AMD and VIA
 Derived from the model numbers of the first few generations of
processors:
• 8086, 80286, 80386, 80486  x86
 Now it generally refers to processors from Intel, AMD, and VIA
• x86-16: 16-bit processor
• x86-32 (aka IA32): 32-bit processor
• x86-64: 64-bit processor
* IA: Intel Architecture
• Intel takes about 80% of the PC market and AMD takes
about 20%
 Apple also have been introducing Intel-based Mac from Nov. 2006
31
Korea Univ
x86 History (Cont.)
4-bit
32-bit
(i586)
8-bit
32-bit
(i386)
16-bit
32-bit
(i686)
64-bit
(x86_64)
2009
Core i7
32
Korea Univ