Transcript Document
Group M3 Jacob Thomas Nick Marwaha Craig LeVan Darren Shultz Project Manager: Zachary Menegakis DSP 'Swiss Army Knife' Final Presentation April 25, 2005 Overall Project Objective: General Purpose Digital Signal Processing Chip Marketing – DSP is Everywhere Marketing – Applications • Audio: – Digital radio, and MP3 players • Apple, Lucent, Motorola, Texas Instruments – Digital music synthesis and sampling • Korg, Yamaha – Noise reduction • Bose, Dolby Marketing – Applications • Video – Video and professional image editing • Apple, Canon, Microsoft, Nikon, – Digital cinema • Sony, Microsoft, Warner Bros., – Video conferencing and IM • AOL, Cisco, Yahoo Marketing – Applications • Telecommunications – VoIP • Bell South, SBC, Verizon, Vonage – Streaming Audio and Video • AOL, Columbia, Sony – Wireless, Cellular • RFID • 802.1x Marketing – Emerging Technologies VoIP: Voice over Internet Protocol transmits audio (human voice, through IP packets (Digital Data) through the internet. In the future this analog to digital conversion will be done within home phones vs. large scale corporate infrastructure. Marketing – MP3 Audio Players Marketing – Biometrics Marketing – System on a Chip (ASIC) • The potential applications of our circuit are vast and diverse – Our circuit is serves as more of a tool for potential clients to implement within their large scale DSP applications. – Ability to vary coefficients and select between 22 different functions of the chip increases usefulness. Marketing – SoftIP • Paper called for complex numbers, this was beyond the scope of this course – Every adder became 2 adders – Every Mult became 4 mults and 2 adds – Total Increase of 60,000 transistors (nearly 100,000 total) • Though our current layout is conducive to audio application, our adaptable soft-IP can gives clients the flexibility to use our design in streaming audio, and streaming video, and other video applications. • Provides perspective customers ability to custom-tailor the chip to their own uses and fab capabilities Emulations - SoftIP Top Level Verilog Verified Complex Function Design Process • Started out with Research Paper on DSP ‘Swiss Army Knife’ – The Swiss Army Knife of Digital Networks by Richard Lyons & Amy Bell • Went through many iterations of modules within design due to complexity of DSP – Required extensive research & meetings with DSP professors & TAs • Simplified the components within our circuit based on focus for Audio w/o imaginary numbers (for hardware) Design Process • Decided on using 12 bit floating point numbers using CMU research on Sphinx Voice Recognition Program • Focused on the major components within our design (FP Multiplier/ FP Add/ Comb) – For floating point multiplier decided to use Booth Recoding to increase complexity & enhance layout • Implemented Full Functionality with Imaginary Numbers in SoftIP • Performed Optimizations – Added Buffers – Reduced White Space Algorithm Floorplan Evolution Full Chip Layout/Floorplan Layer Masks Layout Optimization Verification – Top Level Schematic •Verified all of the functions for the ‘Swiss Army Knife’ in Schematic. •Plotted outputs using custom made code & MatLab. •From plots it is evident that the accuracy is excellent. Verification – fp_mult verilog vs. schematic VSIM 1> run # x xxxxxx xxxxx * x xxxxxx xxxxx = x xxxxxx xxxxx # 0 000000 00000 * 0 000000 00000 = 0 000000 00000 # 0 011110 00000 * 1 011101 11000 = 1 011100 11000 # 0 100001 00100 * 0 100000 01000 = 0 100010 01101 # 0 100001 01110 * 0 100000 00001 = 0 100010 01111 0 100001 11100 * 0 100000 11110 = 0 100011 11010 100100 11110 * 0 100010 11000 = 0 101000 10110 100100 11110 * 1 100010 11000 = 0 101000 10110 100001 00010 * 0 100001 11110 = 0 100100 00000 Note: $finish : fp_mult_tb0.v(41) # Time: 9 ns Iteration: 0 Instance: /tester # #0 #1 #0 # ** Verification – fp_add verilog vs schematic • VSIM 1> # x xxxxxx xxxxx + x xxxxxx xxxxx = x xxxxxx xxxxx # 0 000000 00000 + 0 000000 00000 = 0 000000 00000 # 0 011110 00000 + 1 011101 11000 = 0 011011 00000 # 0 100001 00100 + 0 100000 01000 = 0 100001 11000 # 0 100001 01110 + 0 100000 00001 = 0 100001 11110 # 0 100001 11100 + 0 100000 11110 = 0 100010 01101 # 0 100100 11110 + 0 100010 11000 = 0 100101 00110 # 1 100100 11110 + 1 100010 11000 = 1 100101 00110 # 0 100001 00010 + 0 100001 11110 = 0 100010 10000 # ** Note: $finish : fp_add_tb0.v(40) # Time: 9 ns Iteration: 0 Instance: /tester Verification – Comb ExtractedRC Verification – Top Level ExtractedRC Entire Chip Rise/Fall Time ~ 257 ps Entire Chip Simulation Speed 1 MHz Entire Chip Simulation Time ~ 6 hours Specifications Input Pins (76) X[n] : 12 pins a1, a2, b0, b1, b2: 5 * 12 = 60 pins vdd, gnd, N, c1 : 4 * 1 = 4 pins Output Pins (12) Y[n] : 12 pins Total Pins 88 pins Specifications Floating Point Adder Transistors 2,274 Floating Point Adder Area 103.5450μm x 124.200μm = 12,860.29μm2 Floating Point Adder Density 0.18 Floating Point Multiplier Transistors 2,464 Floating Point Multiplier Area 95.5450μm x 141.750μm = 13,543.50μm2 Floating Point Multiplier Density 0.18 Comb Transistors 6,290 Comb Area 99.360μm x 151.290μm = 15,032.17μm2 Comb Density 0.42 Specifications Entire Chip Transistors 34,564 Entire Chip Area 434.520μm x 395.460μm = 171,835.28μm2 Entire Chip Density 0.20 Flexibility of Design • Example of function 1 of 22: The Moving Averager – Our circuit implements a simple moving average over 8 or 16 data points. – An average is simply the sum of a data set divided by the number of data points. The moving average takes a set number of data points to be used and as new data comes in, old data "falls off" the end of the calculation. For example… Dataflow A Moving Averager Smoothes a Signal to Reduce Noise. • Possible applications or such a function is basic error correction for human machine interfaces Circuit – Animation of Datapath Circuit – Open Sound World Motivation Circuit – Demonstration • Digital amp uses DSP functions to modify the sound. Issues Encountered • DSP Research – Full understanding of complex DSP system prior to beginning layout • Research papers use terminology familiar to the DSP community • Optimizations – Add Buffers from the beginning as more difficult to add at later stages • White Space in Center of Layout – Implemented another iteration of FP Multiplier since it is space limiting block Issues Encountered Entire Chip Floorplan/Layout with Revised FP Mult • • New Specs for Entire Chip with New FP Mult: – Total Chip Area: 142859.60577 – Total Chip Density: 0.22 No More White Space in the Center! Conclusions • DSP is not straightforward – Use faculty resources early in the process • Plan ahead as much as possible, including buffers • Communication is critical • DSP is everywhere! – Including RFID, noise reduction, and wireless communication – Not a niche product, thus large market base and ability to sell large volumes, reducing overall costs.