Transcript set 6 - Waynewolf.us

Topics
Latches and flip-flops.
 RAMs and ROMs.

FPGA-Based System Design: Chapter 3
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Register
Stores a value as controlled by clock.
 May have load signal, etc.
 In CMOS, memory is created by:

– capacitance (dynamic);
– feedback (static).
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Variations in registers
Form of required clock signal.
 How behavior of data input around clock
affects the stored value.
 When the stored value is presented to the
output.
 Whether there is ever a combinational path
from input to output.

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Register terminology
Latch: transparent when internal memory is
being set from input.
 Flip-flop: not transparent—reading input
and changing output are separate events.

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Clock terminology
Clock edge: rising or falling transition.
 Duty cycle: fraction of clock period for
which clock is active (e.g., for active-low
clock, fraction of time clock is 0).

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Registerd parameters
Setup time: time before clock during which
data input must be stable.
 Hold time: time after clock event for which
data input must remain stable.

clock
data
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Dynamic latch
Stores charge on inverter gate capacitance:
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Latch characteristics
Uses complementary transmission gate to
ensure that storage node is always strongly
driven.
 Latch is transparent when transmission gate
is closed.
 Storage capacitance comes primarily from
inverter gate capacitance.

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Latch operation
 = 0: transmission gate is off, inverter
output is determined by storage node.
  = 1: transmission gate is on, inverter
output follows D input.
 Setup and hold times determined by
transmission gate—must ensure that value
stored on transmission gate is solid.

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Stored charge leakage
Stored charge leaks away due to reversebias leakage current.
 Stored value is good for about 1 ms.
 Value must be rewritten to be valid.
 If not loaded every cycle, must ensure that
latch is loaded often enough to keep data
valid.

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Multiplexer dynamic latch
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Non-dynamic latches
Must use feedback to restore value.
 Some latches are static on one phase
(pseudo-static)—load on one phase, activate
feedback on other phase.

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Recirculating latch
Static on one phase:
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Edge-triggered flip-flop
D
Q

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Master-slave operation
 = 0: master latch is disabled; slave latch is
enabled, but master latch output is stable, so
output does not change.
  = 1: master latch is enabled, loading value
from input; slave latch is disabled,
maintaining old output value.

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High-density memory
architecture
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Memory operation

Address is divided into row, column.
– Row may contain full word or more than one
word.
Selected row drives/senses bit lines in
columns.
 Amplifiers/drivers read/write bit lines.

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Read-only memory (ROM)
ROM core is organized as NOR gates—
pulldown transistors of NOR determine
programming.
 Mask-programmable ROM uses pulldowns
to determine ROM contents.

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Flash memory
Flash: electrically erasable PROM that can
be programmed with standard voltages.
 Uses dual capacitor structure.
 Available in some digital processes for
integrated memory, but raises the price of
the manufacturing process.

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ROM core circuit
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SRAM critical path
core
Sense
amp
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Row decoders

Decode row using NORs:
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Static RAM (SRAM)
Core cell uses six-transistor circuit to store
value.
 Value is stored symmetrically—both true
and complement are stored on crosscoupled transistors.
 SRAM retains value as long as power is
applied to circuit.

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SRAM core cell
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SRAM core operation

Read:
– precharge bit and bit’ high;
– set select line high from row decoder;
– one bit line will be pulled down.

Write:
– set bit/bit’ to desired (complementary) values;
– set select line high;
– drive on bit lines will flip state if necessary.
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SRAM sense amp
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Sense amp operation
Differential pair—takes advantage of
complementarity of bit lines.
 When one bit line goes low, that arm of diff
pair reduces its current, causing
compensating increase in current in other
arm.
 Sense amp can be cross-coupled to increase
speed.

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3-transistor dynamic RAM
(DRAM)
First form of DRAM—modern commercial
DRAMs use one-transistor cell.
 3-transistor cell can easily be made with a
digital process.
 Dynamic RAM loses value due to charge
leakage—must be refreshed.

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3-T DRAM core cell
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1-T RAM

1 transistor + 1 capacitor:
word
bit
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1-T DRAM with trench capacitor
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1-T DRAM with stacked capacitor
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Embedded DRAM
Embedded DRAM is integrated with logic.
 DRAM and logic processes are hard to
make compatible.

– Capacitor requires high temperatures that
destroy fine-line transistors.

Embedded DRAM is less dense than
commodity DRAM.
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3-T DRAM operation


Value is stored on gate capacitance of t1.
Read:
– read = 1, write = 0, read_data’ is precharged;
– t1 will pull down read_data’ if 1 is stored.

Write:
– read = 0, write = 1, write_data = value;
– guard transistor writes value onto gate capacitance.



Cannot support full connectivity between all data path
elements—must choose number of transfers per cycle
allowed.
A bus circuit is a specialized multiplexer circuit.
Two major choices: pseudo-nMOS, precharged.
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