Transcript MICROELETTRONICA

MICROELETTRONICA
Design constraints
Lection 5
1
Outline
•
•
•
•
Power dissipation
Interconnect and total delay
Design margin
Reliability
–
–
–
–
–
Electromigration
Self-Heating
Hot carriers
Overvoltage failures
Latchup
• Soft errors
2
Power dissipation
• A) Static Dissipation
– Depends on the leakage currents
Pstatic= IstaticVDD
I static
qV
 KT

 I 0  e  1


-increases as Vt is scaled down
- From gate to source/drain
- From junctions inversely polarized
3
Power dissipation
B) Dynamic dissipation
– Charging and dicharging CL
T
Pdynamic
Pdynamic
T
1
VDD
  iDD  t  VDD dt 
iDD  t  dt

T 0
T 0
VDD
2

Tf swCVDD   CVDD f sw
T
Activity factor α  fsw= αf
C) Short Circuit power dissipation – both transistor conducting
- 10 % Pdynamic
4
Low power design
• Dynamic power reduction
– Reducing activity factor  static logic
– Reducing sizes  effect on logical effort, acceptable
till. 8 -12
– Metrics: power, power-delay, energy-delay
• Static power reduction
– Battery operated systems
– Multiple threshold voltages
5
Interconnect
• Chips are mostly made of wires called
interconnect
– In stick diagram, wires set size
– Transistors are little things under the wires
– Many layers of wires
• Wires are as important as transistors
– Speed
– Power
– Noise
• Alternating layers run orthogonally
6
Wire Geometry
• Pitch = w + s
• Aspect ratio: AR = t/w
– Old processes had AR << 1
– Modern processes have AR  2
• Pack in many skinny wires
w
s
l
t
h
7
Layer Stack
• AMI 0.6 mm process has 3 metal layers
• Modern processes use 6-10+ metal layers
• Example:
Intel 180 nm process
• M1: thin, narrow (< 3l)
– High density cells
• M2-M4: thicker
– For longer wires
• M5-M6: thickest
– For VDD, GND, clk
Layer
T (nm)
W (nm)
S (nm)
AR
6
1720
860
860
2.0
800
800
2.0
540
540
2.0
320
320
2.2
320
320
2.2
250
250
1.9
1000
5
1600
1000
4
3
2
1
1080
700
700
700
700
700
480
800
Substrate
8
Wire Resistance
 r = resistivity (W*m)
r l
l
R
t w
R
w
• R = sheet resistance (W/)
–  is a dimensionless unit(!)
• Count number of squares
– R = R * (# of squares)
w
l
w
l
t
w
l
t
1 Rectangular Block
R = R (L/W) W
4 Rectangular Blocks
R = R (2L/2W) W
= R (L/W) W
9
Choice of Metals
Until 180 nm generation, most wires were aluminum
Modern processes often use copper
Cu atoms diffuse into silicon and damage FETs
Must be surrounded by a diffusion barrier
Metal
Bulk resistivity (mW*cm)
Silver (Ag)
1.6
Copper (Cu)
1.7
Gold (Au)
2.2
Aluminum (Al)
2.8
Tungsten (W)
5.3
Molybdenum (Mo)
5.3
10
Sheet Resistance
Typical sheet resistances in 180 nm process
Layer
Sheet Resistance (W/)
Diffusion (silicided)
Diffusion (no silicide)
Polysilicon (silicided)
3-10
50-200
3-10
Polysilicon (no silicide)
Metal1
Metal2
50-400
0.08
0.05
Metal3
0.05
Metal4
Metal5
0.03
0.02
Metal6
0.02
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Contacts Resistance
• Contacts and vias also have 2-20 W
• Use many contacts for lower R
– Many small contacts for current crowding around
periphery
12
Wire Capacitance
• Wire has capacitance per unit length
– To neighbors
– To layers above and below
• Ctotal = Ctop + Cbot + 2Cadj
s
w
layer n+1
h2
Ctop
t
h1
layer n
Cbot
Cadj
layer n-1
13
Capacitance Trends
• Parallel plate equation: C = eA/d
– Wires are not parallel plates, but obey trends
– Increasing area (W, t) increases capacitance
– Increasing distance (s, h) decreases capacitance
• Dielectric constant
– e = ke0
• e0 = 8.85 x 10-14 F/cm
• k = 3.9 for SiO2
• Processes are starting to use low-k dielectrics
– k  3 (or less) as dielectrics use air pockets
14
M2 Capacitance Data
• Typical wires have ~ 0.2 fF/mm
– Compare to 2 fF/mm for gate capacitance
400
350
300
M1, M3 planes
s = 320
s = 480
s=
200
8
s = 640
Isolated
s = 320
150
s = 480
s = 640
100
s=
8
Ctotal (aF/mm)
250
50
0
0
500
1000
1500
w (nm)
2000
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Diffusion & Polysilicon
• Diffusion capacitance is very high (about 2
fF/mm)
– Comparable to gate capacitance
– Diffusion also has high resistance
– Avoid using diffusion runners for wires!
• Polysilicon has lower C but high R
– Use for transistor gates
– Occasionally for very short wires between
gates
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Lumped Element Models
• Wires are a distributed system
– Approximate with lumped element models
N segments
R
R/N
C
R/N
C/N
C/N
R
R
C
L-model
C/2
R/N
R/N
C/N
C/N
R/2 R/2
C/2
p-model
C
T-model
• 3-segment p-model is accurate to 3% in simulation
• L-model needs 100 segments for same accuracy!
• Use single segment p-model for Elmore delay
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Example
• Metal2 wire in 180 nm process
– 5 mm long
– 0.32 mm wide
• Construct a 3-segment p-model
– R = 0.05 W/
=> R = 781 W
– Cpermicron = 0.2 fF/mm
=> C = 1 pF
260 W
260 W
260 W
167 fF 167 fF
167 fF 167 fF
167 fF 167 fF
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Wire RC Delay
• Estimate the delay of a 10x inverter driving a 2x inverter
at the end of the 5mm wire from the previous example.
– R = 2.5 kW*mm for gates
– Unit inverter: 0.36 mm nMOS, 0.72 mm pMOS
781 W
690 W
Driver
500 fF 500 fF
Wire
4 fF
Load
– tpd = 1.1 ns
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Crosstalk
• A capacitor does not like to change its voltage
instantaneously.
• A wire has high capacitance to its neighbor.
– When the neighbor switches from 1-> 0 or 0->1, the
wire tends to switch too.
– Called capacitive coupling or crosstalk.
• Crosstalk effects
– Noise on non-switching wires
– Increased delay on switching wires
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Crosstalk Delay
Assume layers above and below on average are quiet
Second terminal of capacitor can be ignored
Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors A
B
Cadj
Miller effect
Cgnd
Cgnd
B
Constant
DV
VDD
Switching 0
with A
Switching 2VDD
opposite A
Ceff(A)
Cgnd +
Cadj
Cgnd
MCF
1
0
Cgnd + 2 2
C
21
Crosstalk Noise
• Crosstalk causes noise on non-switching wires
• If victim is floating:
– model as capacitive voltage divider
DVvictim 
Cadj
Cgnd v  Cadj
DVaggressor
Aggressor
DVaggressor
Cadj
Victim
Cgnd-v
DVvictim
22
Driven Victims
• Usually victim is driven by a gate that fights noise
– Noise depends on relative resistances
– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
DVvictim 
Cadj
Cgnd v  Cadj
1
DVaggressor
1 k
 aggressor Raggressor  Cgnd a  Cadj 
k

 victim
Rvictim  Cgnd v  Cadj 
Raggressor
Aggressor
Cgnd-a
DVaggressor
Cadj
Rvictim
Victim
Cgnd-v
DVvictim
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Noise Implications
• So what if we have noise?
• If the noise is less than the noise margin,
nothing happens
• Static CMOS logic will eventually settle to
correct output even if disturbed by large noise
spikes
– But glitches cause extra delay
– Also cause extra power from false transitions
• Dynamic logic never recovers from glitches
• Memories and other sensitive circuits also can
produce the wrong answer
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Wire Engineering
• Goal: achieve delay, area, power goals with acceptable noise
• Degrees of freedom:
– Width
– Spacing
– Layer
– Shielding
0.8
0.7
Coupling:2Cadj / (2C adj+Cgnd)
2.0
1.8
1.6
Delay (ns):RC/2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.6
WireSpacing
(nm)
320
480
640
0.5
0.4
0.3
0.2
0.1
0
0
500
1000
Pitch (nm)
1500
2000
0
500
1000
1500
2000
Pitch (nm)
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Repeaters
• R and C are proportional to l
• RC delay is proportional to l 2
– Unacceptably great for long wires
• Break long wires into N shorter segments
– Drive each one with an inverter or buffer
Wire Length: l
Driver
Receiver
N Segments
Segment
l/N
Driver
l/N
Repeater
l/N
Repeater
Repeater
Receiver
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Repeater Design
• How many repeaters should we use?
• How large should each one be?
• Equivalent Circuit
– Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS = 2W)
• Gate Capacitance C’*W, Resistance R/W
RwlN
R/W
Cwl/2N Cwl/2N
C'W
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Repeater Results
• Write equation for Elmore Delay
– Differentiate with respect to W and N
– Set equal to 0, solve
2 RC 
RwCw
l

N
t pd
l

 2 2
W

RCRwCw
~60-80 ps/mm
in 180 nm process
RCw
RwC
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Reliability
•  Hard errors
• MTBF (Mean Time Between Failures)
• FIT (Failures In Time)
Caused by
• Electromigration
• Self-heating
• Hot carriers
• Latch up
• Overvoltage heating
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Reliability
• Electromigration
– Depends on density of current
– More prone for unidirectional currents
• Self-Heating
– Depends on the dissipation of power which increments
temperature
• Hot carriers
– Depends on the injection of carriers into the gate oxide
– Oxide damaged, reduced current for nMOS, increased current
for pMOS
• Overvoltage failure
– Tiny transistors and Electrostatic discharge  maximum safe
voltage
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Reliability – Latchup
Q1
Q2
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Reliability – Latchup
Starting if VOUT < VSS - 0,7
VBEQ1 > 0,7  electron injection in the base di Q1
and collector (n-well)
Electrons collected by VDD  if Rwell high, VBEQ2
< 0,7V e Q2 in conduction
Holes current is collected by the collector of Q2 (Psubstrate) e da Vss
If Rsubstrate and I high, VBEQ1 >0,7 V more
electrons injected into n-well
.Latchup prevention requires minimization of
Rsubstrate and Rwell
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Soft errors
• Bit flips due to ions, alpha particles, etc.
• Depends on the altitude
• Minimized y maintaining at least some
critical charge on state nodes
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SCALING
34
Transistor scaling
Table 4.15
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Transistor scaling
• Constant field
–
–
–
–
all dimensions are scaled, together with VDD and Vt
NA increased by S
Electric field constant
Cpermicron constant
• Channel length shrink  constant voltage
– Quadretic improvement of delay
– Valid till 1μm for velocity saturation
– Danger of device breakdown
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Interconnect scaling
Table 4.16
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Interconnect scaling
•
•
•
•
Scale all dimensions or wire height constant
Resistance greater as S2 or S
Local wires decrease in length
Effect of aspect ratio
38