Transcript 8th Workshop on Electronics for LHC Experiments

8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Performance of the Beetle
Readout Chip for LHCb
Niels van Bakel, Martin van Beuzekom, Eddy Jans, Sander Klous, Hans Verkooijen
(NIKHEF Amsterdam, Free University of Amsterdam)
Daniel Baumeister, Werner Hofmann, Karl-Tasso Knöpfle, Sven Löchner, Michael Schmelling
(Max-Planck-Institute for Nuclear Physics, Heidelberg)
Ulrich Trunk
(University of Heidelberg)
Neville Harnew, Nigel Smale
(University of Oxford)
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle: Outline
• Beetle Overview
• Beetle 1.2
• Analogue readout
• Front end
• Comparator
• Binary readout
• Pipeamp / Multiplexer
• SEU hard Fast Control / Slow Control
• Results from Total Ionizing Dose (TID)
irradiation test
• Summary
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
2
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle: A Readout Chip for LHCb
• analogue / binary pipeline chip
• providing a prompt binary readout for trigger applications
• integrated in a standard 0.25 µm CMOS technology
• designed for:
Key Specifications:
• Silicon Vertex Detector
• 40 MHz sampling
• Pile-up Veto Trigger
• max. latency 4 µs
• Inner Tracker
• 40/80 MHz readout
• RICH (in case of MAPMTs)
• fast shaping:
• trise  25 ns
• remainder 25 ns after peak  30%
• accept up to 16 consecutive triggers
• readout time  900 ns / trigger
• radiation hard  10 Mrad
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
3
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle: Architecture
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
4
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle: Layout / Floor plan
6.1mm
5.1mm
Layout of the Beetle 1.2 chip and its corresponding floor plan.
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
5
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Analogue readout
• small, but constant baseline dip
• header levels: +/- 42.150 e- (118 e-/mV)
• correct encoded header
Header
1 Start-bit
1 Parity-bit of Pipeline Column Number
1 EDC status-bit
3 different parity-bits of registers
2 LSB-bits of the SEU-counter
8 Pipeline Column Number (PCN) bits
Analogue data
readout on 1 port: 16 bit header, 128 bit data
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
6
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Front end: Pulseshape (1)
peaktime (0-100)
Front end behaviour of the Beetle 1.2
25
(measured with different Cp)
24
peaktime (0-100) [ns]
Ipre=600µA, Isha=80µA, Ibuf=200µA, Vfp=0V, Vfs=0V
40
3pF
gain [mV]
30
51pF
23
22
21
20
20
0
10
10
20
30
40
50
60
Cp [pF]
0
0
25
50
75
100
125
• peaktime  25 ns for Cp  51pF
-10
time [ns]
3pF
13pF
26pF
Performance of the Beetle Readout Chip for
LHCb
36pF
51pF
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
7
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Front end: Pulseshape (2)
risetime (10-90)
18
Front end behaviour of the Beetle 1.2
(measured with different Cp)
risetime (10-90) [ns]
17
Ipre=600µA, Isha=80µA, Ibuf=200µA, Vfp=0V, Vfs=0V
40
3pF
30
51pF
16
15
14
gain [mV]
13
20
12
0
10
10
20
30
40
50
60
Cp [pF]
0
0
25
50
75
100
125
• risetime  17 ns for Cp  51pF
-10
time [ns]
3pF
13pF
26pF
Performance of the Beetle Readout Chip for
LHCb
36pF
51pF
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
8
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Front end: Pulseshape (3)
remainder after 25ns
45
Front end behaviour of the Beetle 1.2
40
remainder after 25ns [%]
(measured with different Cp)
Ipre=600µA, Isha=80µA, Ibuf=200µA, Vfp=0V, Vfs=0V
40
3pF
gain [mV]
30
51pF
20
35
30
25
20
15
10
5
0
0
10
10
20
30
40
50
60
Cp [pF]
0
0
25
50
75
100
time [ns]
13pF
26pF
Performance of the Beetle Readout Chip for
LHCb
• remainder 25 ns after peak is less
than 30% for Cp < 35pF
-10
3pF
125
36pF
51pF
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
9
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Front end: ENC
3.000
preliminary!
2.500
496,7 e + 48,3 e /pF
measured ENC of the new front end on a
complete readout chip Beetle 1.2:
ENC [e]
2.000
Heidelberg: 497 e- + 48.3 e-/pF
1.500
1.000
500
measured ENC of the new front end on a test chip
BeetleFE 1.1:
0
0
10
20
30
Cp [pF]
Performance of the Beetle Readout Chip for
LHCb
40
50
NIKHEF:
Zurich:
Heidelberg:
429 e- + 47.0 e-/pF
436 e- + 47.7 e-/pF
483 e- + 45.7 e-/pF
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
10
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Front end: Dynamic range
Dynamic range for both polarities:
+/- 110.000 e-: < 2% for negative pulses
Beetle 1.2 - Frontend
< 5% for positive pulses
300
DFEout [mV]
200
100
0
-300000
-200000
-100000
0
100000
200000
300000
-100
-200
-300
-400
charge [e-]
Chip 3/1
Performance of the Beetle Readout Chip for
LHCb
Chip 3/2
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
11
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle 1.2: Comparator (1)
• adjustable threshold for each channel
• global threshold
• channel threshold
• Integrator extracts DC-level of shaped
front-end pulse and adds it to threshold
• adjustable time-constant
• mask register for each channel
• multiple operation modes
• digital part is now SEU hard
(triple redundant logic)
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
12
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle 1.2: Comparator (2)
fast LVDS output
signal
track mode
“on” as long as signal is
over threshold
shaped front-end
pulse
very long shaping
pulse mode
“on” only for one BX
one BX dead time
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
13
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Binary readout
• new output buffer for pipelinemode
• no signal spill-over to the
next bunch crossing
Fast comparator output (LVDS signal)
DataVaild (LVDS signal)
Comparator in pipeline-mode
Analogue output pads switched to
LVDS output pads
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
14
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Low trigger rate
Readout at trigger rates of 1 Hz and below
Beetle 1.1
Beetle 1.2
Occurs only in
128 channels
on 1 port
output mode
Floating wire between Pipeamp and MUX
 wrong DC operation point at the
beginning of a readout
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
15
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Output Driver / Modes
• Analogue Output Driver
• bidirectional current driver
• designed to drive analogue signals more than 10 m
• Binary Output Driver
• implemented as LVDS transceiver
• used for the digital pipelined comparator signals
same output pads for
both output drivers
• Modes of output operation
• on 4 ports @ 40 MHz in parallel: readout in 900 ns
• on 2 ports @ 80 MHz in parallel: readout in 900 ns
• on 1 port @ 40 MHz: readout in 3.4 µs (for test purposes)
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
16
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle 1.2: Biasing
• DAC resolution reduced from 10 bit to 8 bit
• Doubled the max. output current of all Current DACs
from 1 mA to 2 mA
• Self triggered, triple redundant flip-flops in all bias
registers => Hardened against SEU
triple redundant flip-flop
with flip indication
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
17
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Fast control / Slow control
• Slow control (I2C-Interface and Register Control)
• Hardened against SEU (state machines use triple redundant flip-flops with majority encoding)
• Hard wired 7-bit Chip Id.
• 20 write- and readable 8-bit registers
• 3 write- and readable mask-registers (in total 641 bits)
• 1 SEU counter (8-bit). (counts all detected and corrected SEU flips).
• Fast control (Pipeline and Readout Control)
• SEU hard
• New reset schema (only one external reset; internal power-up resets all bias and state registers)
• New control schema of the Pipeamp / MUX to prevent the sticky charge problem at low
•
•
•
trigger rates.
Trigger is latched internally (“Trigger phasing”)
Daisy-Chain concept is now implemented
New 8-bit analogue readout header (Start-bit, Parity-bit, EDC status-bit, 3 different parity-bits
of registers, 2 LSB-bits of the SEU-counter)
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
18
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Total Ionizing Dose irradiation
Done at the X-ray facility of CERN‘s Microelectronic Group
Irradiated Chips:
• 4 Beetle 1.1 chips
• 2 chips being kept at room temperature
• 2 chips being annealed at 100 °C
• 2 BeetleFE 1.1 chips
containing FE prototypes with a NMOS input transistor
• 2 BeetleFE 1.2 chips
containing FE prototypes with a PMOS input transistor
Accumulated Dose:
• Beetle 1.1:
• BeetleFE 1.1:
• BeetleFE 1.2:
10 Mrad, 10 Mrad, 30 Mrad, 45 Mrad
10 Mrad
10 Mrad
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
19
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
TID: Results of Beetle 1.1
Beetle 1.1 showed full functionality beyond 45
Mrad
• full trigger and readout functionality
• full slow control functionality
• performance degradations are small
• peaktime: up to 30 Mrad:  1 ns
• gain:
Beetle 1.1
up to 45 Mrad:  4,5 ns
up to 45 Mrad:  10%
no tuning of bias settings
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
20
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Summary
Internal Testpulse
as expected
New Front-end
as expected
Comparator
functionality tested
Pipeamp / MUX
performance problems with consecutive readout
Analogue / Digital Output Driver
as expected
I2C / Slow Control
as expected
Fast Control
OK for LHCb
DACs / Biasing
as expected
New Pads (I2C, CMOS, monitoring-pads)
as expected
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
21
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle Specification: L1 Interface
Rather well defined: http://lhcb-elec.web.cern.ch/lhcb-elec/html/key_parameters.htm
• Bunch crossing rate: 40.08 MHz
• Maximum L0 rate: 1.1 MHz
• L0 latency: 4.0 µs = 160 clock periods
• L0 gap: None
• Consecutive L0 triggers: max. 16
• L0 trigger types: only one (normal trigger)
• Samples to extract per L0 accept: one per channel (multiple samples if required)
• L0 derandomizer depth: 16 events
• L0 derandomizer readout time: (32 + 2 + 2) * 25 ns = 900 ns
• L0 restrictions: emulation of front-end buffers  predictable release of derandomizer buffers
• Bunch crossing clock and L0 distribution: TTC system
• Synchronization checks: all event data must carry synchronization checking data  PCN
• Location and qualification of L0 front-end electronics
• 0.25 µm CMOS technology & special design rules ensure radiation hardness > 10 Mrad
• L1 buffer input speed: 900 ns minimum spacing between events
• L0 front-end reset
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
22
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Specification: Detector Interface
Readout pitch
Signal polarity
Pulse distribution
Mean signal
Detector capacitance
Required S/N
Coupling to detector
Single channel leakage current
Radiation dose
Chip should stand large signals
Distance to next DAQ stage
Required linearity
Signal time jitter
Maximum power consumption
Signal peaking time
Fall time, pulse spill over
Analogue pipeline length
Readout time
De-randomizing buffer
Pile-up Veto
VELO
flexible, 40-60 µm
positive and negative
Landau
11.000 e-/MIP
10 pF
flexible, 40-60 µm
positive and negative
Landau
11.000 e-/MIP
10 pF
> 14, independent from irrad.
AC
0 (AC coupling)
> 2 Mrad/year
up to 400 Mips
10 m
AC
0 (AC coupling)
> 2 Mrad/year
up to 400 Mips
10 m
 25 ns
< 30% after 25 ns
25 ns
-
Performance of the Beetle Readout Chip for
LHCb
Inner Tracker
Landau
11.000 e-/MIP
30 pF
AC
0 (AC coupling)
10 m
 5% ( 10 MIP)
< 5 ns
< 6 mW / channel
< 5 ns
 25 ns
< 30% after 25 ns
160 (4 µs)
900 ns
16 triggers
 25 ns
< 30% after 25 ns
160 (4 µs)
900 ns
16 triggers
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
23
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle 1.2: Comparator (2)
LVDS output signal
shaped front-end pulse
short shaping
track mode
“on” as long as signal
is over threshold
• new output buffer for pipelinemode
• no signal spill-over to the
next bunch crossing
pulse mode
“on” only for one BX
one BX dead time
very long shaping
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
24
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Beetle 1.2: Pipeamp / Multiplexer
Block schematic and timing of
Pipeamp / MUX
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
25
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
TID: Results of Beetle 1.1 (2)
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
26
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
TID: Results of BeetleFE 1.1
only minor performance variations during irradiation
typical slope: 0.1 ns/Mrad
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
27
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Next steps / Outlook
up to now Beetle 1.2 fulfils all LHCb specifications
except for consecutive readouts
Next steps:
• Lab-test of the Beetle 1.2 (readout modes, more pulseshapes,
pipelinehomogenity, ...)
• Random trigger tests
• ENC measurements
• TID irradiation test
• SEU test
• ...
Performance of the Beetle Readout Chip for
LHCb
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
28
8th Workshop on Electronics for LHC Experiments
9-13 September 2002, Colmar, France
Readout
consecutive readout
(no gap between two readouts)
Performance of the Beetle Readout Chip for
LHCb
non-consecutive readout
(minimum gap between two readouts)
Sven Löchner
ASIC-Laboratory, Max-Planck-Institute for Nuclear Physics Heidelberg
29