Transcript Design Process

Presentation #14:
Smart Cart 525
Idongesit Ebong (1-1)
Jenna Fu (1-2)
Bowei Gai (1-3)
Syed Hussain (1-4)
Jonathan Lee (1-5)
Design Manager: Myron Kwai
Stage XIV: 25 April 2005
Final Presentation
Overall Project Objective:
Design a chip as part of a system that accommodates the growing
demand for radio frequency identification (RFID) technology while
creating a quicker, more convenient shopping experience.
Agenda For Final Presentation
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Marketing (Bowei)
Project Description (Syed)
Behavioral/Algorithmic Description (Syed)
Design Process (Jenna)
Floorplan Evolution (Jenna)
Layout (Jonathan)
Issues Encountered (Idong)
Verification (Idong)
Specifications (Jonathan)
Conclusions (Bowei)
Marketing
Bowei Gai
Shop the way YOU want
© 2005 SmartCartGroup
SmartCart525 is a part of a low-cost
solution to today’s shopping
problems utilizing an encrypted,
closed-form, real time
all-in-one reader, and transmitter.
© 2005 SmartCartGroup
Product Need
Problem with Shopping
 Shopping can be wasteful



Time spent waiting in line
Money spent on hiring extra
employees
Retail theft is a $46 billion annual
industry!
RFID Solution
 Like a barcode but…

Omni-directional

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Line of sight not required
Digital accuracy
Availability

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Projected to be on every product
in a few years
$8 billion by 2008
© 2005 SmartCartGroup
The
Solution
We will create an on-cart product monitoring system that will allow for:
•Real-Time shopping
solution
•A Close Form solution requiring
no additional computation
or new shopping carts
•Onboard data encryption
•Reduce of the need for
a check-out system
and personnel
© 2005 SmartCartGroup
The
Edge
Physical
Security
Cost
Aspects
• Advanced
Lightper
$40
weight,
unit
Encryption
small size,
Standard
durable
•
Low production
(Rijndael)
and
Native
• Low
maintenance
Dynamic
power
Public
consumption
cost and
Private
•
Easy implementation
Keys for secure on
data transfer
current
carts and shopping
• Fast and trusted due to
baskets
hardware integration
•••Much
Each
Software
bigger,
cart equipped
encryption
less durable
with
•on-board
•Higher
Slow, power
computationally
laptop
consumption
•intensive
High maintenance
on the processor
cost
Marketing and Exit Strategy
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2 year technical development process
Seek prototype investors for initial funding
Market will be ready for a proven product
Active testing in live retail environments
Outsource and sell to production firm or to be
$$bought out$$ by another company.
Project Description
Syed Hussain
About the Smart Cart 525
Our chip will:
 Take in a 5-bit product ID from RFID receiver to find
product price from a lookup table
 Keep a running total price for items to be purchased
(allows for addition/removal of items from cart)
 Calculate subtotal, tax, total, and take store coupons into
account
 Use Rijndael encryption to securely transmit 32 bit store
card information to store’s central computer
Behavioral/Algorithmic
Description
Main Function
Demux
INPUT
36 Bit Demux
1
Add/Subtract
Add
Subtract
Add Item
Coupon
Lookup price
(Look up
SRAM)
Lookup coupon
(Lookup
SRAM)
Add to total
(Adder)
Money
off
Remove from
total
(2's
compliment
converter,
Adder)
Update
Checkout
Update price in
the SRAM
Apply tax, update
total
(Multiplier, Adder)
Lookup price
(Look up
SRAM)
No op
Encrypt data
Byte Sub
Shift Row
Mix Col
Add round Key
Deduct total
(2's compliment
converter,
Adder)
Percent
off
Calculate
amount off
(Multiplier)
Remove
from total
(2's
compliment
converter,
Adder)
16 bit
Register
Total output
10 bit
Register
Last Item
Price output
OUTPUT
36 bit
Register
Encrypted
data output
PurchaseOrRemove
Lookup Price
(SRAM)
2's Complement
Add 2's
Complement to
Total
Register
Total
Price
DeMUX
Update Price
Update
2:1 MUX
Update Total
Coupon
Lookup Coupon
(ROM)
2's Complement
2:1 MUX
Register
Last
Price
Add 2's
Complement to
Total
Register
32 bit input
Checkout
Register
PurchaseOr
Remove
Register
Operation
Multiply by Total
Add 2's
Complement to
Total
Register
Encrypted
Data
Key Expansion
Encryption
Add RoundKey
Transformation
-ByteSub
-ShiftRow
-MixCol
Add RoundKey
Transformation
-ByteSub
-ShiftRow
Add RoundKey
remove
Purchase
1
Register
Register
PurchaseOrRemove
PurchaseOrRemove
M
PurchaseOrRemove
1
Reset U
X
Read
3
OpCode
PurchaseOrRemove
Item
code
5
goes
high
Register
Register
Lookup
Code
Lookup Code
(Price/Coupon)
(Price/Coupon)
writeEnable
3
OpCode
readEnable
price
10
NewPrice
Reset
Register
16-bit input TotalPriceMUX
13:0
13:0
SRAM
SRAM
~OpCode<2>
enable
OpCode<1>
readEnable
M
LookupCode
5
Reset U
X
Logic
Adder
Adder
5
Lookup code
Lookup code
Enable Write
Enable Write
10
10
M
U
X
7
Add 100
Add 100
7
3
StoreCard15to0
OpCode
16
M
U
X
2
3 Count
OpCode
16
StoreCard15to0
Reset
M
U
X
2
3 Count
OpCode
Check
read
Coupon
store
out price
cardoff
remove
insert
New price
14
14
Multiply Tax by Total
Multiply Tax by Total
21
21
10
StoreCard31to16
Register
3-bit OpCode
Set
10
Register
Register
Checkout
Checkout
3
M
Checkout
Reset U
X
Register
3-bit OpCode
Register
Register
Last
Price
Last
Price
10-bit
10-bit
3
OpCode
3
StoreCard31to16
Reset
Register
Register
Total
Price
Total
Price
21-bit
21-bit
Reset
3
OpCode
Tax?
7
7
Register
Register
NewPrice
NewPrice
M
U
X
14
14
OpCode<2>
TotalPrice
~OpCode<1>
~OpCode<0>
New Price
New Price
10
14
14
3
TotalPriceMUX
OpCode
20:14
20:14
Enable read
Enable read
5
Write
enable
writeEnable
goes
OpCode<0>
high
M
M
U
U
X
X
Register
StoreRegister
Card
Store Card
<31:16>
<31:16>
Register
Store Card
<15:0>
Register
Store Card
<15:0>
Add prices
Done
Inserting
removing
Coupon
shopping/check
an item
off out
inprice
SRAM
Encryption Time
(padded)
Key Expansion
Add RoundKey
Key Expansion
Add RoundKey
Add RoundKey
Transformation
Add RoundKey
Transformation
-ByteSub
-ByteSub
-ShiftRow
-ShiftRow
-MixCol
-MixCol
32
32
Transformation
Transformation
-ByteSub
-ByteSub
-ShiftRow
-ShiftRow
Add RoundKey
Add RoundKey
Register
Register
Encrypted
Encrypted
Data
Data
32-bit
32-bit
Rijndael Encryption 32bit
Generate
different
32bit state
in the
Multiply
column
of
32bit
keysXOR
for
each
Lookup
Table/ROM,
ab XOR’s
1d
byte
matrix,
last
Simple
function,
Add
Key
Byte
Shift
Mixround
Expand:
column:
Sub:
Row:key:
state
matrix,
with
Add
round
Key
replaces
each
byte
with
f0
69
row
interchanged
the
Key
and
the
State
another
function
using
amatrix
new
byte
Wires
ByteSub
and XORS
9 rounds
ab
1d
69
f0
Top Level Schematic
SRAM
Adder
Multiplier
Encryption
Encryption Schematic
KEY
EXPAND
ADD ROUND
KEY
BYTE SUB
SHIFT ROW,
Mix Col
Design Process
Jenna Fu
Design Process

Verilog  schematic  layout
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Behavioral  structural Verilog
Transistors/gates  full schematic
Gate/component layout  top level
Transistor count fluctuated between 17,456-22,434
throughout project
Major design decisions/optimizations
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Reduced 128-bit Rijndael encryption Verilog description to 32bit
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2 ROMS instead of 6 ROMS
Number of inputs
Floating point vs. non-floating point
Eliminating demuxes in encryption (enable/reset registers)
Two clocks (fast/slow)
Floorplan
Floorplan Evolution
(Pre-layout)
Floorplan Evolution
(Mid-layout)
Floorplan Evolution
(Final chip layout)
Layout
Jonathan Lee
Registers
Logic
It’s “Just” Layout
SRAM
Adder
Encryption
Multiplier
Encryption Layout
SBOX with Control Logic
Mix
Key Expand
Column
SBOX
Initial Permutation
Round Permutation
Final Text Out
Issues Encountered/Verification
Idong Ebong
Issues Encountered
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SmartCart525 Warfare Populares
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Productivity falling after a few hours on layout
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Solution is buffing it up with 10 pushups every hour on the hour
Gradually moved up to 40 then laziness kicked in
Minor disliking of the floorplan
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Excellent group dynamic… 90210 style
Need the story, I’ll sign a book deal for some dough
Distrusted the idea of sticking to certain sizes and shapes
Artists need room to expand, dream, and perfect
Tiiiime is on my side… yes it is

No it ain’t
Roadmap to Chip Verification
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LVS issues
Analog Simulation issues
Waveform issues
Verification Lessons
Successful Full Chip verification
Verification Issues
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LVS issues
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Keep track of changes to schematic!!!
Adhere to metal rules to avoid crazy wiring
Watch out for lower level metal contacts
Analog Simulation issues
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Run out of hard drive space after 9h 47m into simulation
Never write your simulation files in notepad
S-R flip flops are not enable flip flops
Arguments on the workings of the SRAM
DC Solution error
Unresolved extraction error
Verification Issues Continued
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Waveform issues
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Vdd drops across M1-M2
contacts too big
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M1 all Vdd
Signal speed distorts results
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Reduce clock speed
Verification Lessons
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Aim for speed. Simulations will not take 1d 37m.
Bother design manager as much as possible and explore
Cadence as much as possible
You will never get a meaningful output first time
Research unknown blocks earlier
Your predicted critical path might not be your real
critical path
You will dream and wish you had more time for a deep
analysis of the design hence try to finish as early as you
can
Successful Full Chip Verification
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Nice Waveform
Matches Schematic and
Extracted Simulations
 Results correct
 Behavioral and Structural
verilog concur
 Happy campers all around
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Ultimate Lesson
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Simulate every step of the
way. Small blocks, top level
schematic, extracted, and
extractedRC multiple times
Specifications
Jonathan Lee
Component Specifications
Encryption
Multiplier
Adder
SRAM
Registers
Transistor
Count
13904
2128
636
2316
2396
Area
(in μm2)
62851
9237
3179
703
8374
Density
0.221
0.230
0.200
0.329
0.286
Final Specifications
Area: 324.765 x 289.89 = 92,879.5 μm2
# of Transistors = 22,120
Density: (transistors/μm2) = .238
Aspect ratio = 1.13
Pin Count = 87 pins
- Input  16-bit input, 3-bit operation code
- Ouput  32-bit textOut, 21-bit finalPrice, 10-bit lastPrice
- vdd!, gnd!, clk, clk2, done
Final Clock Speed: 10MHz with the fast clock running at 50MHz
Conclusion
Bowei Gai
What's Next?
Next Generation System

20 bit FP
adder/multiplier

128 bit encryption.
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No more SRAM, query
from central computer
Our Vision:

Adder/multiplier will get
proportionally bigger.

Encryption logic will
increase proportionally
but SBOX will remain the
same.

Wireless communication
unit will be added to the
system.
Strategies

Understand what’s involved
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Good floorplan
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Detailed specifications. Must meet the specifications.
Leave time for testing

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Good approximations from individual blocks, bit slicing, abutment.
Divide and conquer
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Do the research, is it a reasonable project?
Not done after LVS.
Think ahead, work ahead.
SUCCESS =
TEAMWORK x COMMUNICATION
Road Map for the Restless
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March 26th – Tepper Business Venture
Challenge
April 25th – AMD Sponsored Final Presentation
May 4th – Meeting of the Minds
May 7th – IEEE regional Competition
June 27 – EnterPrize Business Plan
Competition
September 2006- TSMC SmartCart525 Prototype
June 2007- First SmartCart Prototype.