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ECE 636 Reconfigurable Computing Lecture 20 Exam 2 Review Lecture 20: Exam 2 Review November 21, 2013 PRISC ° Architecture: • couple into register file as “superscalar” functional unit • flow-through array (no state) Lecture 20: Exam 2 Review November 21, 2013 PRISC Results ° All compiled ° working from MIPS binary ° <200 4LUTs ? • 64x3 ° 200MHz MIPS base Razdan/Micro27 Lecture 20: Exam 2 Review November 21, 2013 Chimaera • Start from Prisc idea. - Integrate as a functional unit - No state - RFU Ops (like expfu) - Stall processor on instruction miss • Add - Multiple instructions at a time - More than 2 inputs possible • Hauck: University of Washington Lecture 20: Exam 2 Review November 21, 2013 Chimaera Architecture • Live copy of register file values feed into array • Each row of array may compute from register of intermediates • Tag on array to indicate RFUOP Lecture 20: Exam 2 Review November 21, 2013 Chimaera Architecture • Array can operate on values as soon as placed in register file. • Logic is combinational • When RFUOP matches - Stall until result ready - Drive result from matching row Lecture 20: Exam 2 Review November 21, 2013 Chimaera Results • Three Spec92 benchmarks - Compress 1.11 speedup - Eqntott 1.8 - Life 2.06 • Small arrays with limited state • Small speedup • Perhaps focus on global router rather than local optimization. Lecture 20: Exam 2 Review November 21, 2013 Garp • Integrate as coprocessor - Similar bandwidth to processor as functional unit - Own access to memory • Support multi-cycle operation - Allow state - Cycle counter to track operation • Configuration cache, path to memory Lecture 20: Exam 2 Review November 21, 2013 Garp – UC Berkeley • ISA – coprocessor operations - Issue gaconfig to make particular configuration present. - Explicitly move data to/from array - Processor suspension during coproc operation - Use cycle counter to track progress • Array may directly access memory - Processor and array share memory - Exploits streaming data operations - Cache/MMU maintains data consistency Lecture 20: Exam 2 Review November 21, 2013 Garp Instructions • Interlock indicates if processor waits for array to count to zero. • Last three instructions useful for context swap • Processor decode hardware augmented to recognize new instructions. Lecture 20: Exam 2 Review November 21, 2013 Garp Array • Row-oriented logic • Dedicated path for processor/memory • Processor does not have to be involved in array-memory path Lecture 20: Exam 2 Review November 21, 2013 Garp Results • General results - 10-20X improvement on stream, feedforward operation - 2-3x when data dependencies limit pipelining - [Hauser-FCCM97] Lecture 20: Exam 2 Review November 21, 2013 PRISC/Chimaera vs. Garp • Prisc/Chimaera - Basic op is single cycle: expfu - No state - Could have multiple PFUs - Fine grained parallelism - Not effective for deep pipelines • Garp - Basic op is multi-cycle – gaconfig - Effective for deep pipelining - Single array - Requires state swapping consideration Lecture 20: Exam 2 Review November 21, 2013 Common Theme • To overcome instruction expression limits: - Define new array instructions. Make decode hardware slower / more complicated. - Many bits of configuration… swap time. An issue -> recall tips for dynamic reconfiguration. • Give array configuration short “name” which processor can call out. • Store multiple configurations in array. Access as needed (DPGA) Lecture 20: Exam 2 Review November 21, 2013 Observation • All coprocessors have been single-threaded - Performance improvement limited by application parallelism • Potential for task/thread parallelism - DPGA - Fast context switch • Concurrent threads seen in discussion of IO/stream processor • Added complexity needs to be addressed in software. Lecture 20: Exam 2 Review November 21, 2013 FPGA Power Reduction Goals • Dynamic power goals - Reduce Vdd along non-critical paths - Low swing signalling - Use CAD approaches to limit long high-toggle paths - Pdynamic = 0.5 * C * Vdd2 * f • Static power goals - Cut-off Vdd for unused transistors - Use high Vt transistors for SRAM cells - Various other voltage biasing techniques Lecture 20: Exam 2 Review November 21, 2013 Traditional Routing Switch Courtesy: Anderson SRAM cell S S ... CONFIG S S i1 i1 i2 i3 i4 MP2 S MP1 i2 OUT ….. MUX S MUX in VINT i3 S i4 level-restoring buffer Lecture 20: Exam 2 Review November 21, 2013 Proposed Switch Designs: Anderson ° Based on 3 observations: • Routing switch inputs tolerant to weak-1 signals (level-restoring buffers). • Considerable slack in FPGA designs many switches can be slowed down. • Most routing switches feed other routing switches. - Can produce weak-1 logic signals. Lecture 20: Exam 2 Review November 21, 2013 “Basic” Switch Design CONFIG SRAM cell S S ... VDD S VDD MNX MPX ~SLEEP LOW_POWER v SLEEP VVD VVD i1 i2 i3 i4 OUT ….. MUX GND in MODE OPERATION: Lecture 20: Exam 2 Review LOW_POWER s GND ~LOW_POWER high-speed: MNX & MPX ON low-power: MNX ON, MPX OFF sleep: MNX OFF, MPX OFF November 21, 2013 High-Speed Mode CONFIG SRAM cell S S ... VDD S VDD MNX MPX ~SLEEP LOW_POWER v SLEEP VVD = VDD VVD i1 i2 i3 i4 OUT ….. MUX output swing: rail-to-rail. GND in MODE OPERATION: Lecture 20: Exam 2 Review LOW_POWER s GND ~LOW_POWER high-speed: MNX & MPX ON low-power: MNX ON, MPX OFF sleep: MNX OFF, MPX OFF November 21, 2013 Low-Power Mode CONFIG SRAM cell S S ... VDD S VDD MNX MPX ~SLEEP LOW_POWER v SLEEP VVD = VDD - VTH VVD i1 i2 i3 i4 OUT ….. MUX GND in LOW_POWER s ~LOW_POWER output swing: output swing: GND-toGND-to(VDD -VTH). GND (VDD-VTH). high-speed: MNX & MPX ON MODE OPERATION: low-power: MNX ON, MPX OFF sleep: MNX OFF, MPX OFF Lecture 20: Exam 2 Review November 21, 2013 Sleep Mode CONFIG SRAM cell S S ... VDD S VDD MNX MPX ~SLEEP LOW_POWER v SLEEP VVD VVD i1 i2 i3 i4 OUT ….. MUX GND in LOW_POWER s GND ~LOW_POWER high-speed: MNX & MPX ON MODE OPERATION: low-power: MNX ON, MPX OFF November 21, 2013 Lecture 20: Exam 2 Review sleep: MNX OFF, MPX OFF Leakage Power Results: Anderson % leakage power reduction vs. high-speed mode 70 60.8 Basic 60 50 39.7 40 36 38.7 30 20 10 0.3 0 LP mode Lecture 20: Exam 2 Review Sleep mode LP mode (+unused fanout) LP mode (+used fanout) Traditional switch November 21, 2013 FPGA Embedded Memory Blocks ° Embedded memory blocks (EMBs) are important parts of FPGAs ° Consume roughly 14% of Altera Stratix II dynamic power * • Increasing in recent designs * Stratix II Low Power Applications Note, 2005 Lecture 20: Exam 2 Review November 21, 2013 Embedded Memory Block Port Internal View Clk Enable Bit Line Pre-charge MClk MClk Clk BIT BIT RAM cell Row Decode Column Mux Write Buffers Sense Amps MClk Write Enable MClk Address Read Enable MClk Latch Read Data Write Data Reducing clocking saves dynamic power Lecture 20: Exam 2 Review November 21, 2013 Power Optimization #1 ° Convert EMB read enable/write enable signals to associated read/write clock enable signals ° Limitations • Each port has read or write enable control signal • Embedded memory block has read enable input Before Data Vcc Wren Write Address Data Wr clk enable Write enable After Q Rd clk enable Vcc Read enable Rden Write Read Address Address Clock Lecture 20: Exam 2 Review Q Read Address Data Wren Vcc Write Address Data Wr clk enable Write enable Q Q Rd clk enable Rden Read enable Vcc Write Read Address Address Read Address Clock November 21, 2013 Implementation ° Conversion mode • Ties off R/W enable to RAM clock enables • Doesn’t make transform if CE already present on port ° Combining mode • AND user RAM clock enables with derived R/W clock • Could impact performance Write Enable User-defined Write Clk Enable Lecture 20: Exam 2 Review Combined Write Clk Enable November 21, 2013 FPGA RAM Processing FIFO, Shift Register, RAM specification Create Logical Memory Logical-tophysical RAM processing Logical RAMs/ logic Memory/ logic placement Placed Memory RAM blocks/ logic ° FIFOs and Shift registers converted into logical RAMs ° Logical RAMs mapped to RAM blocks Lecture 20: Exam 2 Review November 21, 2013 Mapping RAM to EMBs ° Implementation choice can impact design area, performance, and power. ° Some mappings may require multiple EMBs User-defined (logical) memory 16K bits 4k deep x 4 wide Physical (EMB) memory 4K bits 4K bits 4K bits 4K bits M4K M4K M4K M4K 512K MRAM Lecture 20: Exam 2 Review November 21, 2013 Memory Organization ° Each EMB can be configured to have different depth and width (e.g. Stratix II M4K) 4K words deep 128 words deep 512 words deep 32 bits wide 8 bits wide 1 bit wide ° All hold 4K bits ° Slightly lower power consumption for wider EMB configurations (not including routing) Lecture 20: Exam 2 Review November 21, 2013 Area and Delay Optimal Mapping ° Configure each EMB to be as deep as possible ° Number of address bits on each EMB same as on logical memory ° Area and performance efficient: no external logic needed ° Power inefficient: All EMBs must be active during each logical RAM access Vertical Slicing Logical memory 4k words deep and 1 bit wide (4 times) 4k words deep and 4 bits wide 4 EMBs active during access Addr[0:11] EMB Data[0:3] Lecture 20: Exam 2 Review November 21, 2013 Alternative Mapping ° Configure EMB to have width of logical RAM (e.g. 1Kx4) • Allows shutdown of some RAMs each cycle • But adds some logic ° Saves RAM power, adds combinational logic and register power Addr[10:11] Horizontal Slicing Addr Decoder 1K deep x 4 wide More Power Efficient: Logical memory (4 times) Addr[0:9] 1 EMB active during access 4k words deep and 4 bits wide 4 Addr[10:11] Data[0:3] Lecture 20: Exam 2 Review November 21, 2013 RAM Slicing - Example ° Power reduction available with different slicing 4kx32 Dynamic Power Dynamic Power (mW) Multiplexer Power Increasing 140 Best range 120 100 80 60 40 20 0 128 256 512 1k 2k 4k EMB Power Increasing Maximum Depth Lecture 20: Exam 2 Review November 21, 2013 Power Optimization #2: Power-aware RAM Partitioning FIFO, Shift Register Create Logical Memory Power-aware Physical RAM processing Power Library Insert Decode and Mux Logic Memory/ Logic Placement Completed placement ° Algorithm considers possible logical to physical RAM mappings Lecture 20: Exam 2 Review November 21, 2013 Experimental Approach ° 40 designs evaluated ° Quartus 5.1 ° Mapped to smallest possible device and target max frequency ° Simulation with test vectors ° Power analysis with PowerPlay Lecture 20: Exam 2 Review November 21, 2013 Experimental Approach ° 40 designs evaluated ° Quartus 5.1 ° Mapped to smallest possible device and target max frequency ° Simulation with test vectors ° Power analysis with PowerPlay Lecture 20: Exam 2 Review November 21, 2013 Memory Power ° 21.0% average reduction for all techniques (9.7% with convert/combine) 80 Enable convert/ combine % Dyn Power Reduction 70 60 Enable convert/ combine + Mem partition 50 40 30 20 10 0 -10 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Designs Lecture 20: Exam 2 Review November 21, 2013 Overall Core Dynamic Power ° 6.8% average power reduction for all techniques (2.6% with convert/combine) 35 Enable convert/ combine % Dyn. Power Reduction 30 Enable convert/ combine + mem partition 25 20 15 10 5 0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 -5 Designs Lecture 20: Exam 2 Review November 21, 2013 39 Design Performance ° 1.0% average performance loss for all techniques (0.1% for enable convert/combine) Average Design Clock Frequency 10 % Frequency Improvement 5 0 -5 -10 Enable Convert/ Combine -15 Enable Convert/ Combine + Mem Partition -20 -25 -30 Designs Lecture 20: Exam 2 Review November 21, 2013 Results Summary ° Almost 7% core dynamic power reduction across all designs • Some designs benefit more than others ° Minimal clock frequency hit for most designs Enable convert Enable convert/ combine Enable convert/ combine + Mem partition -1.8% -2.6% -6.8% Memory dynamic power -6.3% -9.7% -21.0% Max clk freq -0.1% -0.2% -1.0% LUT count 0.0% 0.1% 0.7% Core dynamic power Lecture 20: Exam 2 Review November 21, 2013 Other material ° Lecture 17: Reconfigurable Memory Security ° Lecture 18: Hardware Monitors to Protect Network Processors ° Lecture 19 is not covered on the exam Lecture 20: Exam 2 Review November 21, 2013