Transcript Evelyn Hu (UCSB)

IC-DFN Workshop
Hangzhou, August 15, 2006
Designing for Uncertainty: Critical Issues for New
Nanoelectronic Technologies
Evelyn L. Hu
California NanoSystems Institute
UCSB
UNCERTAINTIES
A Few Candidate Technologies
• Technologies for post-CMOS?
• Architectures for new technologies
–Too early to extract device parameters?
Seeds of an architecture
Plan large-scale systems?
with defect tolerance
– Uncertainties in device variability, failure modes
• Where are the sources of errors in system operation,
in fabrication?
Beginnings….
Are We Finally at the Limits?
www.intel.com
Challenges to Further
Scaling (CMOS)
• Fundamental Physical Limits?
•
•
•
Intel 45 nm Shuttle Test Chip
– Leakage through dielectric
– Small current drive, electron
statistics
– Thermal noise
– Interconnect delay
High densities -> severe power
dissipation
Complexities in design &
verification
Economic Limits: the cost of
reliable fabrication
The Next Technology Generation
Continued faster, better (functional), cheaper
•
Performance
–
–
–
–
•
Faster access time
Low power
Operates over wide temperatures
Non-volatile
Manufacturability
–
–
–
Robust process latitude
Low-cost fabrication
Scalability
CHOICES? Benchmarks?
Selecting a post-CMOS Technology:
choices
• Limitations of present (scaled) technology
– Cross talk
– Leakage
– Charge modulation: statistical limitations of dopants
– Maintaining high noise margins at reasonable temperatures
• Desired scalability
– Scale down in size: fabrication at the nanoscale
– Scale up in complexity
 Increased alignment accuracy
 Issues of interconnect delay
Selecting a post-CMOS Technology:
Choices
Single Electron
• Address limitations
Transistors
– Leakage
– Cross talk
Quantum Cellular Automata
– Charge modulation: statistical
Spintronics:
limitations of dopants
alternative
– Maintaining high noise
‘state variables’
margins at reasonable temperatures
Simplify
• Desired scalability
manufacturability
– Scale down in size: fabrication at
Molecular Electronics
the nanoscale
– Scale up in complexity
Carbon Nanotube
 Increased alignment accuracy
 Issues of interconnect delay
transistors
No one technology addresses ALL the challenges, or provide ALL
the desirable features for the next-generation technology
Limiting Leakage: Single
Electron Transistors
electron
EC = Q2/2C;
Q = charge,
C = capacitance
ETh ~ kT; EC >> kT
For a small enough ‘island’ and very small
capacitance, C, and for Ec >> Eth,
THERE IS AN ENERGY COST TO ADDING
OR REMOVING CHARGE FROM THE ISLAND
(no leakage)
Limiting Leakage: Single
Electron Transistors
Ea = single-electron addition energy
electron
For a small enough ‘island’ and very small
capacitance, C, and for
Ec >> Eth, THERE IS AN ENERGY COST
TO ADDING OR REMOVING CHARGE
FROM THE ISLAND (no leakage)
Likharev, Electronics Below 10 nm
Room temperature (25 meV) operation only
possible for island diameter ~ few nanometers
Taking Advantage of Crosstalk:
Quantum Cellular Automata
QCA Cell:
Quantum dots with excess charge
Charge distribution
from electrostatic repulsion
Addition of charge -> changed
charge distribution, cellular ‘state’;
‘0’
‘1’
Majority Gate Device
Truth Table
Amlani et al., Science 284, 280 [1999]
(Notre Dame)
Nearest-neighbor interaction,
Fabrication & scale-up challenging, room temperature
operation unlikely
local computation
Operation at Room Temperature:
Magnetic Cellular Automata
Applied magnetic field
Cowburn & Welland,
Science 287, 1466 [2000]
Input dot = ‘0’
Input dot = ‘1’
 Larger magnetic quantum dots
(110 nm diameter),
 Material: Ni80Fe14Mo3X
 Propagation of information through
exchange interaction between dots
 Elongated dot, injector
Using Spin to Transfer
Information
GaMnAs Digital Alloys
David Awschalom,
Art Gossard
UCSB
Spintronic Technology
Spin-based Devices
Ferromagnetic spin filter
Semiconductor
Nanoscale-engineered
materials
Detector (Quantum well)
New device concepts
Powerful
new information
technologies
 Experiments have shown long spin coherence lifetimes, but…
 Need to understand best material systems and device configurations
 Mechanism of control: Magnetic (e.g. MCA) or electronic?
Selecting a post-CMOS Technology:
Choices
Single Electron
• Address limitations
Transistors
– Leakage
– Cross talk
Quantum Cellular Automata
– Charge modulation: statistical
Spintronics:
limitations of dopants
alternative
– Maintaining high noise
‘state variables’
margins at reasonable temperatures
• Desired scalability
– Scale down in size: fabrication at
the nanoscale
 Challenges in device
– Scale up in complexity
 Increased alignment accuracy
 Issues of interconnect delay
fabrication profound
 Limited architectures for
large scale systems
Incorporating natural nanoscale building blocks:
Carbon Nanotubes



Beautiful structural order in carbon
nanotubes
Exceptional electrical properties
A single carbon nanotube can be made into a
transistor
Chen et al., Science 311, 1735 [2006]
or a ring oscillator
 Can dope single carbon nanotube
both n-type and p-type
 Enhanced compactness, multifunctionality
Challenges: control of conductivity,
doping, assembly
Incorporating natural nanoscale building blocks:
molecular switches
wire
Apply electric
signal
wire
Stoddart & Heath, UCLA
With very dense nanowires (20 nm)
in cross-bar geometry
HP has taken these concepts to
larger-scale arrays, considered
architectures and defect tolerances
Developing the Molecular
Crossbar Platform
Wu et al., Applied Physics A
80, 1173 [2005]
Cross-bar configuration, with
molecular interlayer
34 x 34 cross-bar memory,
30 nm half-pitch, Ti/Pt wires
 I-V of single device:
HYSTERETIC SWITCHING
 On= 1.5 positive bias, top
electrode; Off = negative bias
 ON/OFF ~ 10
HP has used this architecture
for memory (a) and logic (b)
(a) Chen et al., Nanotechnology14, 462 [2003]; (b) G. Snider, Applied Phys.A 80, 1165 [2005]
Sample of ‘defect-tolerant’ nano-architecture
Lay out demultiplexer
circuit on crossbar
geometry
Kuekes et al,
Appl. Phys.A 80, 1161 [2005]
address
signal
Defect
‘stuck open’
Demux circuit
(not defect-tolerant)
Defect-tolerant circuit
2-bit address passes through
CMOS encoder -> 3 bit encoded address
6-bit signal vector u -> redundant input
address
Sample of ‘defect-tolerant’ nano-architecture
Calculated percentage of
usable nanowires, versus
defect probability for
different levels of
redundancy, d (address
bit)
Summary and Beginnings
Technologies for post-CMOS?
 A wide variety of candidates, at different levels of maturity
 No one technology addresses ALL the challenges, or provide
ALL the desirable features for the next-generation
technology
 Architectures for new technologies
 Initial work on cross-bar geometry with molecular switches
 Simple architectures, error-tolerant schemes provide
important benchmarks
 Consideration of appropriate architectures CRITICAL (even
in the face of uncertainty) to help sort and direct progress
of technology

Selecting a post-CMOS Technology:
Choices
Single Electron
• Address limitations
Transistors
– Leakage
– Cross talk
Quantum Cellular Automata
– Charge modulation: statistical
Spintronics:
limitations of dopants
alternative
– Maintaining high noise
‘state variables’
margins at reasonable temperatures
Simplify
• Desired scalability
manufacturability
– Scale down in size: fabrication at
Molecular Electronics
the nanoscale
– Scale up in complexity
Carbon Nanotube
 Increased alignment accuracy
 Issues of interconnect delay
New Opportunities in Resilient, Manufacturable
Information Systems?
The Emergent Integrated Circuit of the Cell
Hanahan & Weinberg, Cell [2000]
transistors