Transcript 10a-technology

MOS Technology
 Underlying implementation technology of virtually all hardware
components in wide-spread use today
 Obeying Moore's law
 doubling density and performance every 18 months
 certain to continue for the next decade
 fundamental limits will be reached soon
 Understanding of abstract technology provides insight into tradeoffs
inherent in hardware design
CSE 567 - Autumn 1998 - CMOS I - 1
MOS as an Abstract Technology
 Transistors are switches (first-order approximation)
 Two types of transistors are possible
n-type:
gate
drain
p-type:
drain
"0"
"1"
open
closed
"0"
"1"
closed
open
source
gate
source
 All logic can be built from these simple primitives
CSE 567 - Autumn 1998 - CMOS I - 2
MOS Technology –
Metal/Oxide/Semiconductor
 Multiple layers of material on a silicon substrate with intervening insulation
 Substrate is a silicon lattice with doping ions in selected locations
 Layers in substrate include n-type and p-type regions
 Layers above substrate are polycrystalline silicon, metal (Al, W, or Cu), etc.
 Insulating layers is silicon oxide (SiO2 or glass)
diffusion
poly
side view
cuts
top view
CSE 567 - Autumn 1998 - CMOS I - 3
metal
MOS Technology (cont'd)
 Layers can be used to electrically connect signals (routing)
 Layers above substrate are medium to excellent conductors
 Layers in substrate are poor conductors (doped semiconductor)
 Substrate and silicon oxide are excellent insulators
 Interaction between polycrystalline silicon (poly) and diffusions creates the
transistor that is key to building logic structures
thin oxide between
poly and diff
form transistor
CSE 567 - Autumn 1998 - CMOS I - 4
MOS Transistors
 Two types of diffusion – silicon has 4 electrons in valence shell
n-type – doping ions have extra electrons (5 valence, phosphorus)
p-type – doping ions have extra holes (3 valence, boron)
 Polysilicon over substrate (separated by thin layer of silicon oxide) is used
to form channel between two regions of same type of diffusion
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CSE 567 - Autumn 1998 - CMOS I - 5
Realities of MOS Transistors
 n-type devices pass "0"s well –– p-type devices pass "1"s well
 a "1" is 5v and a "0" is 0v in current CMOS technology (moving to 3v)
 gate to source voltage (Vgs) must be greater than 1v for n-type device to
start conducting (less than -1v for p-type device)
gate
drain
when Vg=Vd=5v,
source
Vs won't go higher than 4v
gate
when Vg=Vd=0v,
drain
source
Vs won't go lower than 1v
(note: drain and source are symmetric)
CSE 567 - Autumn 1998 - CMOS I - 6
Switching Logic
conducts iff
a•b
(0 only)
a
a
b
s
conducts iff
a+b
(0 only)
d
d
s
b
a
s
conducts iff
a'•b' or (a+b)'
(1 only)
a
b
d
d
s
b
CSE 567 - Autumn 1998 - CMOS I - 7
conducts iff
a'+b' or (a•b)'
(1 only)
Implementation of Logic Gates
 OR gate
a
1
f(a,b)
b
a
b
a+b
0
0
0
0
1
1
1
0
1
1
1
1
 Two problems
 1) when a=b=0, f(a,b) is undefined (floating)
 2) n- type switches do not conduct 1 well
 Two solutions
 when f=0, connect output to 0v using n-type switches
 when f=1, connect output to 5v using p-type switches
CSE 567 - Autumn 1998 - CMOS I - 8
Complementary CMOS Gates
 Pull-up network consisting of p-type devices
5v (logic 1)
 Pull-down network consisting of n-type devices
P
inputs
output
N
 Example: an inverter
a
a'
0
1
1
0
0v (logic 0)
: a'
a
pull-up
a'
: a
CSE 567 - Autumn 1998 - CMOS I - 9
pull-down
CMOS NOR Gate
 f(a,b) = (a+b)'
a
b
f
0
0
1
0
1
0
1
0
0
1
1
0
a
: a'•b'
: a+b
b
a
b
note that these
are complements
of each other
CSE 567 - Autumn 1998 - CMOS I - 10
General CMOS Gate
 Use De Morgan's Law
:
f(x)
:
f'(x)
 Example:
:
:
f(a,b,c) = (a•b+c)'
(a•b+c)' = (a'+b')•c'
a•b+c
a
b
c
f
a
c
b
CSE 567 - Autumn 1998 - CMOS I - 11
Complex Gates
 AND-OR-Invert (AOI) for SOP
 OR-AND-Invert (OAI) for POS
 Any function without internal inversions
f = a(b'+cd)
CSE 567 - Autumn 1998 - CMOS I - 12
Switch Logic vs. Gate Logic
 Example: two-input multiplexer
a
2:1
b
f
f=a,
when s=0
f=b,
when s=1
f=s'a+sb
s
CSE 567 - Autumn 1998 - CMOS I - 13
Switch Logic vs. Gate Logic (cont'd)
 Two-input mux with gate logic (14 transistors)
 Two-input mux with switch logic (6 transistors)
complementary
pass transistor
CSE 567 - Autumn 1998 - CMOS I - 14
Switches and Gates
 Another example: 4-to-1 multiplexor
sum-of-products form
implementation with NAND gates
32 transistors + 4 for control
F = AS1'S0' + BS1'S0 + CS1S0' + DS1S0
A
A
B
C
D
F
B
F
C
D
S1
S0
S1
CSE 567 - Autumn 1998 - CMOS I - 15
S0
4:1 Multiplexor (cont'd)
 Using switch logic
A
B
F
F
C
D
S1
S0
S1
12 transistors + 4 for control
16 transistors + 4 for control
CSE 567 - Autumn 1998 - CMOS I - 16
S0
4:1 Multiplexor (cont'd)
 Mixed design
A
B
F
C
D
If A, B, C, and D are busses
of many wires then the
multiplexor structure will be
replicated and should be
made as small as possible
even at the expense of extra
control logic (it will only be
needed once).
S1
S0
8 transistors
CSE 567 - Autumn 1998 - CMOS I - 17
Exploiting Switch Logic
 Carry-out of full-adder – implement with gates or switches
G
OR
(ab)'
(ab)'
Cin
Cout
ab
P
CSE 567 - Autumn 1998 - CMOS I - 18
a'b'
K
Implementing Look-up Tables (LUTs)
 Multiplexor logic – simple switch network (a tree)
 inputs: programming bits
 controls: inputs to CLB
Bit0 Bit1 Bit2
 output: function value
 However, series transistors
are slow – O(n2)
Bit3 Bit4 Bit5 Bit6 Bit7
A'
A
B'
B
C'
C
F
CSE 567 - Autumn 1998 - CMOS I - 19
Implementing Programmable Interconnect
 Switches connect wires at intersections
 Can also be used to segment wire
 Repeaters needed every so often
 simple non-inverting buffers (2 inverters)
 otherwise, too many switches in series slow down signal
CSE 567 - Autumn 1998 - CMOS I - 20