Transcript ppt

Silicon Detectors
for Tracking and Vertexing
Andrei Nomerotski,
University of Oxford
INSTR08, Novosibirsk
29 February 2008
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Andrei Nomerotski
Silicon Detectors
 Using silicon diode as s detector

1951: first observation of signals in reversely biased p-n
junction from a’s
 Development for tracking stimulated by need to
measure short-lived charm/beauty quarks and tau
lepton in ’70
 1980, J.Kemmer: first proposed to use planar process
developed in industry to produce strip silicon detectors


Fast, localized charge deposition  3 micron intrinsic
resolution
Planar process  dimensions precise to 1 micron, low cost
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Andrei Nomerotski
Vertex Detectors
 SLD data events with clear primary (left) and
secondary (right) vertices
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Andrei Nomerotski
Trackers
200 MeV protons hitting CMS pixel module at shallow angle
(Roland Horisberger, PSI)
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Andrei Nomerotski
Silicon for Vertex Detectors
 Resolution at IP for two layers with resolution s
  r1/r2 should be as small as possible

for s=10 mm, r1/r2=0.5, sb = 20 mm
 multiple scattering  r2 can’t be large
Beampipe f 5 cm, thickness 1 mm Be = 0.3% X0
  28 mm at IP for P = 1 GeV

Two conclusions
First layer as close as possible to Interaction Point
As thin as possible
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Andrei Nomerotski
Silicon for Tracking
 Precise measurement of
curvature  excellent
momentum resolution
 Low occupancy per strip 
excellent pattern recognition
2D  3D information
 Strip detectors: ghosts
complicate pattern
recognition
 Pixel detectors – best
possible pattern recognition
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Andrei Nomerotski
Strip Detectors
 Depleted p-n diodes
 Fast and efficient charge
collection by drift in electric
field

4 fC in 300 micron of Si
 Each strip has capacitance to
backplane and neighbours
 Noise is typically dominated
by serial contributions 
scales with detector
capacitance
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Andrei Nomerotski
Strips vs Pixels
 Strip detectors
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Large capacitance, 10 pF
Large signal, 24000 e
Large noise, 2000 e
 Pixel detectors
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 Well established area –
dozens of small, large and
huge trackers and vertex
detectors in operation since
’90
 New development: strips in
depth of sensor – 3D silicon
strips
Small capacitance
Extra low noise, 10-100 e
Could do with small signal
 Opens variety of
interesting options
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Andrei Nomerotski
Pixel Detectors
 Hybrid pixels – well established for LHC
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Solder
bump
Bump bonding
Sophisticated electronics
 Collect charge from thinner sensors  use
wafers with 5-25 micron epi-layer, closer to
industry mainstream

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CMOS and CCD based detectors
Collect by diffusion in reasonable time, 100 ns
Readout
 First move charge to the side
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CCD
Silicon Drift detectors
 Integrate electronics and detector – a
lot of interesting recent developments
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Andrei Nomerotski
Outline
New requirements for next generation machine for Particle Physics
(LC and SLHC)
New technologies available in industry
Column Parallel CCDs
Storage Pixel Detectors, ISIS
Fine Pixel CCDs
Chronopixels
Vertical integration of sensors and electronics
Silicon On Insulator
DEPFET
Silicon Drift Detectors
System issues
Silicon Tracker for ILC
Material
Serial Powering
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Applications
Andrei Nomerotski
I will not discuss in this talk :
 Active Pixel Sensors (APS)

Talk by Lars Eklund
 3D and active edge silicon

Talk by Daniel Pennicard
 LHC and other existing trackers / vertex detectors

Multiple talks in this session
 Radiation hardness issues

Review by Gianluigi Casse
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Andrei Nomerotski
Linear Collider : Precise Thin Detectors
ILC physics demands excellent
Vertexing (b,c,t) and Tracking
30% E
Vertex detector characteristics
point resolution 3 mm
Thickness ~ 0.1 % X0
5-6 layers
Inner radius ~ 1.5 cm
t t event at 350 GeV
d (IP) < 5 mm  10 mm/(p sin3/2 q)
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(best SLD 8 mm  33 mm/(p sin3/2 q))
Andrei Nomerotski
Linear Collider Physics Case
 Higgs:
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Model independent observation
Establish mass generation
mechanism
 SUSY
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Symmetry breaking mechanism
Measure properties of
supersymmetrical particles
 Precision

Access to higher energy scale
Will require
excellent flavour ID
Higgs can be reconstructed through
recoil mass independently of its decay
channel
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b c light
Flavour Identification
 Main motivation for vertex detector
for LC
 Combine several variables into
Neural Net
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Vertex mass – main contributor
Vertex momentum
Decay length
Decay length significance
Jet Probability
LCFI collaboration
 Vertex charge
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Charge of tracks associated to vertex
Allows to distinguish between b and
anti-b quarks
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The Readout Challenge
LC Beam Time Structure:
0.2 s
337 ns
2820x
0.95 ms = one train
What readout speed is needed?
 Massive e+e- background from beamstrahlung : pairs
radiated in intense EM fields of bunches
 Need to read out once occupancy = 1%

20 times per train = 20 kHz per 1 Mpixel frame
 Different approaches
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Time stamping
In situ storage
Rolling shatter
Super-fine segmentation
Andrei Nomerotski
Column Parallel CCD
LCFI develops CCD (Charged Coupled Device) based sensors
M
M
N
N
“Classic CCD”
Readout time 
NM/fout
Column Parallel
CCD
Readout time = N/fout
Readout time shorten by orders of magnitide
Need 50 MHz clock to achieve 20 kHz / frame
Main difficulty: distribution of 20 A clocks at 50 MHz
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CPC2
ISIS1
CPC2-70
Busline-free CPC2
104 mm
CPC2-40
LCFI
CPC2-10
● CPC2 wafer (100 .cm/25 μm epi and
1.5k.cm/50 μm epi)
Second generation CPCCD sensor: CPC2
The whole image area serves as a
distributed busline
Designed to reach 50 MHz operation
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Andrei Nomerotski
CPCCD Testing
 Achieved low-noise operation
at 20 MHz
 Used CPR2 to read out and
CPD1 to drive large devices
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CPD1 provides 20 A clock at
50 MHz
CPR2 : 128 ADC, cluster
finding and sparse readout,
works at 9 MHz
CPD1
CPC2-40
CPR2
LCFI
Pedestal
peak
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Photopeak
Amplitude spectrum of 5.9 keV 55Fe X-rays at 20 MHz
Andrei Nomerotski
CPCCD with Low Capacitance
LCFI
● New
ideas to reduce high CCD capacitance
● Open phase CCD, “Pedestal Gate CCD”, “Shaped Channel CCD”
● Could reduce Cig by ~4
● e2V Technologies produced 27 types of small CCDs to check these
ideas
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Andrei Nomerotski
ISIS
– In-Situ Storage Image Sensor
ISIS1 “proof of principle”
constructed at e2V
LCFI
 Each pixel has internal memory implemented as CCD register
 Charge collected under a photogate
 Charge is transferred to 20-pixel storage CCD in situ
 Conversion to voltage and readout in the 200 ms-long
quiet period after collision
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Andrei Nomerotski
ISIS Proof of Principle
LCFI
Tests with 55Fe X-ray source:
 ISIS1 with and without p-well tested
 Correct charge storage in 5 time slices and consequent readout
 Charge collection through photogate demonstrated
 Tested in testbeam in 2007
 ISIS2 design in preparation, submission in April 2008
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Andrei Nomerotski
Fine Pixel CCD
 Idea: use pixel of ~5mm to keep occupancy low
 Fully depleted epitaxial layer to minimize the number of hit pixels due to
charge spread by diffusion
 Accumulate hit signals for one train (1 ms) and read out between trains (200
ms)  should be very robust
 Results for test structures: possible to deplete fully
 S7170 SPL24mm, highest resistivity 24mm thick epi-layer, Hamamatsu
 Used laser to induce signal
Y. Sugimoto, KEK
Projection
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Next generation FPCCD
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7.5 mm
12mm pixel size
24mm epitaxial layer
512x512 pixels
6.1mm2 image area
4 different design of output
amp
 To be delivered at the end of
2007
Y. Sugimoto, KEK
8.2 mm
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Integration of Sensor and Electronics
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Chronopixels (MAPS type)
U.Oregon, Yale, Sarnoff
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What is 3D Circuit Integration?
Optical Fiber In
 A 3D chip is comprised of
several layers of semiconductor
devices which have been
thinned, bonded together, and
interconnected to form a
“monolithic” circuit.
Four Key Enabling Technologies
 Wafer thinning (to <25mm)
 Precision alignment

Optical Fiber O
Opto Electronics
Digital layer
Analog Layer
50 um
Sensor Layer
Designer’s Dream
Better than 1 micron
 Bonding of thinned wafers
 Interconnection of wafers by
metal vias
All possible now
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Andrei Nomerotski
3D Integration is Future Mainstream in
Industry
 Industry is moving toward 3D to improve circuit performance.

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Reduce R, L, C for higher speed
Reduce chip I/O pads
Provide increased functionality
Reduce interconnect power and crosstalk
 Utilizes technology developed for Silicon-on-Insulator devices
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Andrei Nomerotski
Examples of 3D Sensor Integration
8 micron pitch, 50 micron thick oxide bonded
imager (Lincoln Labs)
Epoxy bonded 3D connected imager
(RTI/DRS)
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8 micron pitch DBI (oxide-metal) bonded
PIN imager (Ziptronix)
Andrei Nomerotski
Silicon on Insulator
 Thin active circuit layer on an
insulating substrate

~200 nm of silicon on a
“buried” oxide (BOX) on a
“handle” wafer.
(Soitech illustration)
 The handle wafer can be high
quality, detector grade silicon
 Opens the possibility of
integration of electronics and
fully depleted detectors



in a single wafer
with very fine pitch
little additional processing.
 Important for 3D integration
Active
BOX
Substrate
(detector material)
Steps for SOI wafer formation
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Andrei Nomerotski
Key Technologies for SOI/3D
1) Bonding between layers
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bond
Oxide to oxide fusion
Copper/tin bonding
Polymer/adhesive bonding
2) Wafer thinning

SiO 2
Grinding, lapping, etching
Polymer
(BCB)
Cu
Sn
3) Through wafer via formation
and metallization
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Cu3Sn
(eutectic bond)
Direct bond
interconnect
With isolation
Without isolation
4) High precision alignment
SEM of 3 vias
using Bosch
process
Via using
oxide etch
process
(Lincoln
Labs)
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Thin Silicon
 After silicon is thinned to 50 micron or less it
becomes flexible and eventually transparent
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SOI Concept for HEP
Minimal interconnects,
low node capacitance
not to scale
High resistivity
Silicon wafer,
Thinned to 50100 microns
R.Lipton, R.Yarema (Fermilab)
Backside implanted after thinning
Before frontside wafer processing
Or laser annealed after processing
Active edge
processing
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3D Pixel Design for ILC Vertex Detector
R&D program at Fermilab


Goal - demonstrate ability to implement a complex pixel design with all
required ILC properties in a 20 micron square pixel
Previous technologies limited to very simple circuitry or large pixels
 3D chip design using MIT Lincoln Labs 0.18 um SOI process.
 3D density allows analog pulse height digitization, sparse
readout, high resolution time stamp, all in a 20 micron pitch
pixel.
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Time stamping and sparse readout occur in the pixel, Hit address found
on array perimeter
64 x 64 pixel demonstrator version of 1k x 1K array
Submitted to 3 tier DARPA multi project run at LL
 Sensor to be added later
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Andrei Nomerotski
3D Geometry
Pad to sensor
Tier 3
Sample 1
Sample
1
Sample
2
Delay
Vth
S. Trig
To analog output buses
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Tier 2
Digital time stamp bus
Write data
Analog T.S.
b0 b1 b2 b3 b4
Read data
Analog ramp bus
Chip designers:
Tom Zimmerman
Gregory Deptuch
Jim Hoff
Analog time output bus
In
Inject
Test input S.R.
pulse
Out
Y address
X address
D FF
Data clk
Tier 1
Token In
Pixel
skip
logic
Q S
R
Token out
Read
all
Read data
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Andrei Nomerotski
 Pixel cell
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Tot 175 transistors in
20x20 µm pixel
3 Tiers with tot 22 µm
height
Unlimited use of PMOS
and NMOS
Allows 100 % diode fill
factor
 Received back in Nov
2007, testing underway
Full 3D Pixel Circuit
20 um
Tier 3
Tier 2
Tier 1
High resistivity substrate
BOX
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Andrei Nomerotski
Depleted FET
J. Kemmer & G. Lutz, 1987
DEpleted P-channel FET
Row wise read-out ("rolling shutter")

select row with external gate, read current, clear
DEPFET, read current again  the difference is
the signal
gate
DEPFET- matrix
reset
off
off
on
reset
off
off
nxm
pixel
off
off
VGATE, ON
VGATE, OFF
IDRAIN
drain
VCLEAR, ON
VCLEAR, OFF
VCLEAR-Control
0 suppression
output

fully depleted sensitive volume, charge collection by drift

internal amplification  q-I conversion: 0.4 nA/e, scales with gate length and bias current

Charge collection in "off" state, read out on demand
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DEPFET: Noise versus bandwidth
High speed readout => high bandwidth => short shaping times
Thermal noise of the DEPFET transistor ~ 1/SQRT(t)
1.6 e ENC at t=10 ms
25 e ENC at t=33ns (30MHz)
MPI, Germany
Measurements of a single pixel with an external high bandwidth amplifier.
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DEPFET Testbeam
MPI, Germany




Pixel size 36 x 28.5 mm2
Timing 320 nsec
S/N = 110
Resolution 2 mm
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Andrei Nomerotski
Silicon Drift Detectors
 p+ segmentation on both sides
of silicon
 Complete depletion of wafer
from segmented n+ anodes on
one side
 Distance measured by drift
time
 Small load capacitance –
excellent noise performance
 Position resolution

2 mm in lab, 10 mm in testbeam,
30 mm in experiments
 Applications

SDD fully functioning in STAR
SVT since 2001, will be used
by ALICE (1.3 m2)
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Andrei Nomerotski
Controlled Drift Detector
 Channel stops confine
charge to parallel
drifting channels
 Potential minimum near
top surface
 Control of drift field:
“integrate-readout”
modes
 Similar to CCD but
charge moved by
constant field
 Drift time 1-2 ms/cm


20 mm in 2-4 ns
CPCCD 20 mm in 20 ns
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CDD Results
 Produced prototypes with
6.1 mm drift length
 Compton electron and
other types of imaging
with excellent position and
timing resolution
 Design of 10.2 mm long
drift detector (1x3 cm2
total area) in progress
(COMPTON, INFN
Milano)
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System Issues
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Silicon Tracker for ILC
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Silicon Tracker for ILC
 Modules overlap to eliminate
projective cracks
 Sensors are ~92mm on a side
 Each sensor has is readout
independently by KPIX chip

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Bump bonded directly to sensor
0.2 x 0.5 mm2 readout cells
T.Nelson, SLAC
 4 layer Cu / kapton cable that
carries power, signals, and bias
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Andrei Nomerotski
Thinning Technology at MPI
Semiconductor Laboratory
1) Process backside of thick detector wafer
(structured) implant.
sensor wafer
handle wafer
sensor wafer
2) Bond detector wafer on handle wafer (SOI).
sensor wafer
1. implant backside
on sensor wafer
3) Thin detector wafer to desired thickness (grinding
& etching).
handle wafer
HLL
sensor wafer
1. implant backside
on sensor wafer
2. bond sensor wafer
to handle wafer
1. implant backside
on sensor wafer
handle wafer
2. bond sensor wafer
to handle wafer
2. bondHLL
sensor wafer
to handle wafer
3. thin Industry:
sensor side Trac
to desired thickness
Industry: TraciT, Grenoble
3. thin sensor side
to desired thickness
4) Process front side of the detector wafer in a
standard (single sided) process
line.
handle wafer
HLL
Industry: TraciT, Grenoble
sensor wafer
1. implant backside
on sensor wafer
2. bond sensor wafer
to handle wafer
3. thin sensor side
to desired thickness
5) Etch handle wafer.
If necessary:
Al-contactsIndustry: TraciT, Grenoble
handleadd
HLLwafer
Leave frame for stiffening and handling, if wanted
1. implant backside
on sensor wafer
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2. bond sensor wafer
to handle wafer
3. thin sensor side
to desired thickness
4. process DEPFETs
on top side
4. process DEPFETs
on top side
HLL main lab
4. process DEPFETs
on top side
5. structure resist,
etch backside up
to oxide/implant
HLL main lab
HLL special lab
5. structure resist,
etch backside up
to oxide/implant
Andrei Nomerotski
Thinning : mechanical samples
6” wafer with diodes and large mechanical samples
Thinned area: 10cm x 1.2 cm (ILC vertex detector dummy)
Possibility to structure handling frame
(reduce material, keep stiffness)
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Andrei Nomerotski
Mechanics: Foams
 Goal : 0.1% X0
 Properties:

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Open-cell foam
Macroscopically uniform
No tensioning needed
 Good results with 3% RVC
(Reticulated Vitreous Carbon)
prototype
 Also: Silicon Carbide foam
LCFI
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Andrei Nomerotski
Power Distribution
 Power is a crucial issue for the vertex detector
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
CP CCD 20 amps x 200 modules = 4000 amps of clock
MAPS or SOI 20-100W x 100(DF)@1V = 2000 - 10,000 amps
 Vertex detector technology is sexy - but power
engineering is just as important

Serial powering (think Xmas lights) can lower instantaneous
current

Understand noise, engineer regulators, understand interconnects

Or/and DC-DC converters

Lower CCD capacitance
Routing in and out


Include something capable of providing 2-10kW in simulation
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Andrei Nomerotski
Serial Power
Atlas SLHC design but
applicable elsewhere
Initial tests indicate good
noise performance
• Instantaneous power = average power x (50-100) 20W ave.=>2kW
• At 1.5 V peak current ~666 A, 3 cm diam. of copper/side needed for 50mV drop
• Serial powering can reduce peak currents
– Requires individual ladder regulators (3D integrated?)
– V*n, I/n, V tolerances relaxed with local regulation
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DC-DC Converters
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Applications
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X-Rays in Silicon
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Visible photon range few mm
20keV X-ray range 5 mm
100 keV X-ray range 80 mm
For larger energies need different
materials (higher Z)
6 keV X-rays, 1 ms exposure time
(Cornell)
Appl. Phys. Lett. 83 (2003) 1671
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Andrei Nomerotski
MAMBO - Monolithic Active pixel Matrix with
Binary cOunters in SOI Technology OKI 0.15µm
 Counting pixel detector with
integrated readout for X-ray or
electron microscope imaging

Similar to Medipix but
monolithic
 64x64 26x26 mm pixels
 12-bit counter, 1 MHz
 350 mm thick sensor
total: 280 transistors
 First version produced and
tested in 2007


good separate performance of
analogue and digital parts
Second version submitted to
OKI
G.Deptuch, Fermilab
26 x 26 mm2
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Andrei Nomerotski
Preservation of Mechanical Recording
Disc: groove moves from side to side
Audio is encoded in micron scale features
which are >100 meters long
• Used ATLAS silicon module
survey camera for scanning
• Software filters out noise
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Andrei Nomerotski
Summary
 Tracking and Vertexing by precise silicon detectors is
a mature field
 Ramping up efforts on integration of detectors and
electronics
 Is it a ladder for a future vertex detector?
Ladder ?
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Andrei Nomerotski