Transcript Diez-TIPP11

System implications of the different powering
distributions for the ATLAS Upgrade strips
tracker
Summarized by S. Díez-Cornell
June 11, 2011
Outline
• Motivation
• The silicon strip tracker of ATLAS Upgrade
• Power architectures
• Studies
• Summary and conclusions
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Motivation: HL-LHC, ATLAS Upgrade, Si tracker
 HL-LHC: 10x increase of luminosity wrt LHC (~1035 cm-2·s-1)
– More events on the detectors => Higher hit density
• Faster detectors and electronics
• More channels => Higher power demands, material budget constraints,
space for services limited
 New powering schemes for on-detector electronics
 ATLAS ID has to be redesigned and rebuilt completely
 Silicon tracker: upgraded tracker for the ATLAS detector
– Inner tracker: Si pixel detector
– Outer tracker: Si strips tracker
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Silicon strips tracker
 Si strip sensors arranged in double-sided layers of “staves” (barrel) and
“petals” (end-caps)
*
 Numerous sensor modules per stave and petal side:
472 double-sided
half-staves
Half- Stave: 12
modules/side
Short strip stave
*
* From D. Santoyo & R. Marco, IFIC
320 double-sided
petals
Petal: 9 modules/side
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Silicon strips tracker: sensor modules
 Sensor module prototypes:
Short strips
• Strip sensor (2.5 (SS) & 10 (LS) cm barrel, 2.7 to 5.4 cm endcaps)
• Readout hybrids (10 ROICs + 1 HCC/hybrid)
• Readout chip: ABC-Next (130 nm CMOS)
–
–
Binary readout
256 channels/ABCN
»
Power consumption estimates: ~ 250 mW/ABCN (< 1mW /ch)[1]
 Analogue (1.2 V): ~ 280 μW/ch
 Digital (0.9 V): ~ 360 μW/ch
Long strips
• Hybrid Controller Chip (HCC)
–
Power consumption estimations: ~ 180 mW (0.9 V) [2]
• Still a “conceptual” idea
– Current prototypes under test are with ACBn25
ASICs (250 nm CMOS, 128 channels/chip):
[1] F. Anghinolfi, ABCn development, ATLAS Upgrade Week, Oxford, 2011
[2] P. Farthouat, ATU-SYS-ER-0004, 2010
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Power architectures
• Independent powering (as in SCT)
1
2
3
4
5
6
n-1
n
……
Hybrid current = I
Number of hybrids =n
Total current = nI
Power lines = n
……
• Serial powering
Hybrid current = I
Number of hybrids =n
Total current = I
Power lines = 1
1
*r = voltage conversion ratio
3
4
5
Constant
current
source
1
Constant
(high)
voltage
source
6
n-1
n
……
• DC-DC powering
Hybrid current = I
Number of hybrids =n
Total current = n(I/r*)
Power lines = 1
2
2
3
4
5
6
n-1 n
……
+-
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Serial powering
GND
– Constant current along the chain, equal to the hybrid current
– Shunt transistors and low-dropout regulators (LDOs) provide hybrid
voltage
• Shunt regulator shunts excessive hybrid current, “recycled” in the serial
power line
• LDOs derive locally analogue/digital voltage in the ABCns
• Several possible configurations
– Each module at a different ‘GND’  AC coupling required for control
and data lines
– Is = Ih (constant)
– Vs = n·Vh
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DC-DC powering
+-
– Parallel powering of each module
– 2-step voltage conversion:
• 1st step: Buck DC-DC converters (1 per module)
– Inductor as energy storage unit and switch power transistors
– Voltage conversion ratio = g (typically between 4 and 6)
• 2nd step: Step-down switched capacitors (1 or 2 per ABCN)
– Voltage conversion ratio = w (typically 2 – 2.5)
• Total conversion ratio = r = g·w (typically between 8 and 10)
– IS = n·(Ih/r) = n·(Ih/(g·w))
– VS = r·VABCn (constant)
– 2nd step may not be possible on-chip due to noise on ABCn internal power
buses coming from switched caps
• Currently under investigation
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Module prototypes
 Module prototypes built and being tested with both power
configurations:
LBNL
• Individual modules:
 Liverpool (SP & DC-DC)
 Berkeley Lab (SP)
 Geneva (DC-DC)
 Oxford (SP)
 BNL (SP)
 Cambridge, Santa Cruz,
DESY, Freiburg, Glasgow, …
• “Stavelet”:
Liverpool
 RAL (SP)
• Under construction:
 DC-DC powered stavelets
 “Petalet” (endcaps)
RAL
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Power efficiency (I)
• Barrel modules:
– Serial powering:
•
•
•
•
•
Analogue voltage derived from shunts, digital from LDOs
Shunt regulator efficiency = 85% [3]
LDOs dropout voltage = 0.3 V
Estimated ε = 69 % (no trace/cable losses)
Total power per stave = 62 W
IS (constant) = 2.15 A
…
Vh = 1.2 V
VS = 29 V
– DC-DC powering:
•
•
•
•
•
•
1st step (buck converters) delivers 2.4 V
2nd step (switched caps) delivers 1.2 - 0.9 V
Buck converters efficiency = 85% [4]
Simulated switched caps efficiency = 97% [5]
Estimated ε = 82 % (no trace/cable losses)
Total power per stave = 53 W
IS = 5.3 A
VS (constant) = 10 V
[3] M.Newcomer, , ATLAS Upgrade Week, Oxford, 2011
[4] G. Blanchott, ATLAS Upgrade Week, Oxford, 2011
[5] M. Bochenek and F. Anghinolfi, ATLAS Upgrade Week, Oxford, 2011
…
Ih = 0.22 A
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Power efficiency (II)
• Endcap modules
– Non uniform within the same petal
• Different hybrid and sensor sizes  different capacitive loads
– Serial powering:
• ε = 56% (no trace/cable losses)[6]
• Total power per petal = 30.7 W
• Current in the line defined by the
biggest hybrid (10 ABCns)
VS = 13.2 V
• High LDO losses
IS (constant) = 2.14 A
– DC-DC powering:
• ε = 78% (no trace/cable losses)[6]
• Total power per petal = 22.3 W
VS (constant) = 12 V
IS = 1.85 A
[6] From C. Friedrich (DESY, Berlin) and R. Marco (IFIC)
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Noise studies
•
Results with latest ABCN250 stave module and stavelet prototypes from Liverpool, RAL
and Geneva
– Evidences of (low) noise signatures related to powering in the modules
– Similar input noise both for serial and DC-DC with current module prototypes: ~ 600 – 615 e at 1
fC [7]
• No additional noise introduced by serial power protection circuit
• EM noise from inductors and switching noise minimized with optimized shielding (Cu tape)
for DC-DC
– Serially and DC-DC powered stavelets show no additional noise wrt individual modules [8]
Serial
DC-DC
615e
608e
601e
Channel number
590e
Input noise (e-)
Input noise (e-)
620e
599e
590e
603e
[7] From A. Affolder and A. Greenall (Univ. Liverpool)
[8] P. Phillips, ATLAS Upgrade Week, Oxford, 2011
Channel number
12
System protection and reliability
•
Serial powering:
– Need to protect serial power chain in case of open circuit, noisy module, …
– Power Protection Board (PPB) + Serial Power Interface (SPi) allow slowcontrol and real time bypass modules within a SP chain
– Designed, fabricated, and successfully tested with RAL stavelet[9]:
All hybrids on
V = 22.7 V, I = 5.09 A
Slow control disables odd hybrids
V = 12.7 V, I = 5.09 A
– SPP ASIC currently under design, to be submitted this year
•
DC-DC powering:
– Protection components implemented in buck converter ASIC prototype
(AMIS4, submitted Jan 2011)[10]
• Over current, over temperature, input under-voltage
• Soft start state machine for reliable start-up procedure
[9] D. Lynn et al., NIMA 633, 51-60 (2011)
[10] G. Blanchott, ATLAS Upgrade Week 2011
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Material budget
•
•
Last material estimations for ABCN130 short strips stave
module[11]:
Serial powering:
– 1 control and 1 protection ASIC/hybrid, shunts, included
– Bus traces not included
• % X0 = 0.03 to stave, coming from extra hybrid area and
AC-coupling caps
PPB
39x6 mm2
SPP ASIC
 Assuming 10% higher power dissipation for serial than DC-DC
on the stave: effect on (as-built) stave core ~ 0.02% /0.01%
additional from StSt/Ti cooling pipes
•
DC-DC:
– Buck ASIC, PCB (Cu), custom inductor (Cu), inductor
Shielding (Cu), included
– Switched capacitors not included
– Bus traces for DC-DC power not included
• % X0 = 0.23 to stave, coming from capacitors, buck PCB,
inductor and shield
Buck DC-DC converter
13x28 mm2
 This number could be reduced by the use of Al instead of Cu
on several components of the buck converter, studies underway
[11] A. Affolder and T. Jones, ATLAS Upgrade Week , Oxford, 2011
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Service needs and cable reuse
• LV cable needs:
– DC-DC powering:
• 1 power line per stave, ~ 5 A for short strips
• End of Stave (EoS) boards included in the power scheme
– Serial powering:
• 1 power line per stave ~ 2 A for short strips
• EoS boards not included in the serial power chain
Additional power line ~ 0.8 A
• Two possible reuse scenarios, both of them feasible in principle:
– Scenario 1: Reuse SCT cables
• Enough cable count, but Cu cross-section not sufficient for acceptable voltage drop
– Need to combine several cables in patch panels
– Scenario 2: Reuse TRT Cables
• Enough Cu cross-section, but cable count not sufficient
– Need to redistribute Cu cross-section
– ONLY LV cables considered here!
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Summary and conclusions
Serial powering
DC-DC powering
Efficiency (barrel)
69%
82%
Efficiency (endcaps)
56%
78%
Input noise
~600e-
~600e-
Protection
PPB, SPI, SPP ASIC, …
Over-I, Over-T, soft start, …
Material budget
0.03 %X0
0.23 %X0
Services
Higher count, lower power losses
Lower count, higher power losses
• Serial and DC-DC powering architectures still considered for the
strips
• Both options seem still feasible, no evident show stopper
• Preferably same power distribution for barrel and endcap…
• Upcoming prototypes will allow a more straightforward comparison
• No final conclusion yet
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Backup slides
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ATLAS Si tracker “Strawman” layout (2008)
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Slow control and real time response
D. Lynn et al., NIMA 633, 51-60 (2011)
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Buck DC-DC converter
From C. Haber, Silicon detectors course, TIPP-2011
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Service needs & cable reuse
• LV cable needs:
Serial
DC-DC
Number Voltage (V) Current (A) Number Voltage (V) Current (A)
Short strips
432
29
2.15
432
10
5.3
Barrel Long strips
512
14.5
1.5
512
10
1.9
EoS boards
944
2.5
0.8
2.5
0.8
Strips
640
13.2
2.15
640
12
1.85
Endcaps
EoP boards
640
2.5
0.8
2.5
0.8
TOTAL
3168
1584
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