Soft Error Rate Determination for Nanometer
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Transcript Soft Error Rate Determination for Nanometer
Soft Error Rate Determination for
Nanometer CMOS VLSI Circuits
Fan Wang
Vishwani D. Agrawal
Department of Electrical and Computer Engineering
Auburn University, AL 36849 USA
40th Southeastern Symposium on System Theory
March 16-18, 2008
SSST'2008
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Outline
Background
Problem Statement
Analysis
Results and Discussion
Conclusion
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Motivation for This Work
With the continuous downscaling of CMOS technologies,
the device reliability has become a major bottleneck.
The sensitivity of electronic systems can potentially
become a major cause of soft (non-permanent) failures.
The determination of soft error rate in logic circuits is a
complex problem.
It is necessary to analyze circuit reliability. However,
there is no comprehensive work that considers all the
factors that influence the soft error rate.
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Strike Changes State of a Single Bit
10
Definition from NASA Thesaurus:
“Single Event Upset (SEU): Radiation-induced errors in microelectronic
circuits caused when charged particles [also, high energy particles]
(usually from the radiation belts or from cosmic rays) lose energy by
ionizing the medium through which they pass, leaving behind a wake
of electron-hole pairs”.
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Impact of Neutron Strike on a Silicon Transistor
neutron strike
source
Strikes release electron
& hole pairs that can be
absorbed by source &
drain to alter the state of
the device
drain
+
+ - - ++
- Transistor Device
Neutron is a major cause of electronic failures at
ground level.
Another source of upsets: alpha particles from
impurities in packaging materials.
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Cosmic Rays
p
p
n
n
p
n
n
p
n
Earth’s Surface
p
n
Source:
Ziegler et al.
Neutron flux is dependent on altitude, longitude, solar activity etc.
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Problem Statement
Given background environment data
Neutron flux
Background energy (LET*) distribution
*These two factors are location dependent.
Given circuit characteristics
Technology
Circuit netlist
Circuit node sensitive region data
*These three factors depend on the circuit.
Estimate neutron caused soft error rate in standard FIT** units.
*Linear Energy Transfer (LET) is a measure of the energy transferred to the device
per unit length as an ionizing particle travels through material. Unit: MeVcm2/mg.
**Failures In Time (FIT): Number of failures per 109 device hours
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Measured Environmental Data
Typical ground-level neutron flux: 56.5cm-2s-1.
J. F. Ziegler, “Terrestrial cosmic rays,” IBM Journal of Research and
Development, vol. 40, no. 1, pp. 19.39, 1996.
Particle energy distribution at ground-level:
“For both 0.5μm and 0.35μm CMOS technology at
ground level, the largest population has an LET of 20 MeVcm2/mg or less. Particles with energy greater than 30
MeV-cm2/mg are exceedingly rare.”
Probability density
K. J. Hass and J. W. Ambles, “Single Event Transients in Deep Submicron
CMOS,” Proc. 42nd Midwest Symposium on Circuits and Systems, vol. 1,
1999.
0
15
30
Linear energy transfer (LET), MeV-cm2/mg
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Proposed Soft Error Model
Occurrence rate
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Pulse Widths Probability Density Propagation
fX(x)
Delay
τp
1
Dout
X
Y
fY(y)
0
τp
2τp
Din
We use a “3-interval piecewise linear” propagation model
1) Non-propagation, if Din ≤τp.
2) Propagation with attenuation, ifτp < Din < 2τp.
3) Propagation with no attenuation, if Din 2τp.
Where
Din: input pulse width
Dout: output pulse width
τp : gate input output delay
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Validating Propagation Model Using HSPICE
Simulation
Simulation of a CMOS inverter in TSMC035 technology with load
capacitance 10fF
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Pulse Width Density Propagation Through
a CMOS Inverter
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Soft Error Occurrence Rate
Calculation for Generic Gate
PSEU PSEU (1)
i
EMR j [Pnoncontrollin g (i)]
electrical_ masking
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logic _ masking
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SER Results on Workstation Sun Fire 280R
Circuit
#PIs
C17
5
2
6
0.01
0.3679
C432
36
7
160
0.04
1.0563
C499
41
32
202
0.14
0.2188
C880
60
26
383
0.08
0.3882
C1908
33
25
880
1.14
0.7427
C2670
233
140
1193
0.77
0.2882
C5315
178
123
2307
2.78
0.5572
C7552
207
108
3512
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#POs #Gates CPU s
FIT/gate
/output
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10.82 0.6652
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SER Results for Inverter Chains
Circuit
#PIs
#POs
Inv2
Inv5
Inv10
Inv20
Inv50
Inv100
1
1
1
1
1
1
1
1
1
1
1
1
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#Gate
s
2
5
10
20
50
100
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CUP
(s)
0.00
0.00
0.00
0.00
0.00
0.04
FIT/gate
0.2819
0.5388
0.9654
1. 8185
4.3780
8.6473
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Result Comparison
Logic Circuit SER Estimation
Ground Level
Measured Data
Devices
SER*
(FIT/Mbit)
0.13µ SRAMs [2]
10,000 to
100,000
SRAMs, 0.25μ and
below [3]
10,000 to
100,000
1 Gbit memory in
0.25µ [4]
4,200
Our Work
1,000 to
10,000
Rao et al. [1]
1x10-5 to 8x10-5
The altitude is not mentioned for these data.
[1] R. R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, “An Efficient Static Algorithm for
Computing the Soft Error Rates of Combinational Circuits," Proceedings of the conference on
Design automation and test in Europe, pp. 164-169, 2006.
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Conclusion
SER in logic and memory chips will continue to
increase as devices become more sensitive to soft
errors at sea level.
By modeling the soft errors by two parameters, the
occurrence rate and single event transient pulse
width density, we are able to effectively account for
the electrical masking of circuit.
Our approach considers more factors and thus gives
more realistic soft error rate estimation.
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References
[2] J. Graham, “Soft errors a problem as SRAM
geometries
shrink,“http://www.ebnews.com/story/OEG200201
28S0079, ebn, 28 Jan 2002.
[3] Wingyu Leung; Fu-Chieh Hsu; Jones, M. E.,
"The ideal SoC memory: 1T-SRAMTM," Proc.13th
Annual IEEE International on ASIC/SOC
Conference, pp. 32-36, 2000
[4] Report, “Soft Errors in Electronic Memory-A
White Paper," Technical report, Tezzaron
Semiconductor, 2004.
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