Transcript Lecture 25a

Lecture #25a
OUTLINE
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Interconnect modeling
Propagation delay with interconnect
Inter-wire capacitance
Coupling capacitance effects – loading, crosstalk
Transistor scaling
Silicon-on-insulator (SOI) technology
Interconnect scaling
Reading (Rabaey et al.): Sections 3.5, 3.6.
Note that he has an entire chapter (4 – The Wire) devoted to
interconnects in which he elaborates on some of the slides in
this lecture.
Note also pp. 229-232 – Perspective and Summary
EECS40, Fall 2004
Lecture 25a, Slide 1
Prof. White
Interconnects
• An interconnect is a thin-film wire that electrically
connects 2 or more components in an integrated circuit.
• Interconnects can introduce parasitic (unwanted)
components of capacitance, resistance, and inductance.
These “parasitics” detrimentally affect
– performance (e.g. propagation delay)
– power consumption
– reliability
• As transistors are scaled down in size and the number of
metal wiring layers increases, the impact of interconnect
parasitics increases.
→ Need to model interconnects, to evaluate their impact
EECS40, Fall 2004
Lecture 25a, Slide 2
Prof. White
Interconnect Resistance & Capacitance
Metal lines run over thick
oxide covering the substrate
VDD
 contribute RESISTANCE
& CAPACITANCE to the
output node of the
driving logic gate
PMOS
NMOS
GND
EECS40, Fall 2004
Lecture 25a, Slide 3
Prof. White
Wire Resistance
Rwire
L
L

 Rs
HW
W
L
H
W
EECS40, Fall 2004
Lecture 25a, Slide 4
Prof. White
Interconnect Resistance Example
Typical values of Rn and Rp are ~10 kW, for W/L = 1
… but Rn, Rp are much lower for large transistors
(used to drive long interconnects with reasonable tp)
Compare with the resistance of a 0.5mm-thick Al wire:
R•=  / H = (2.7 mW-cm) / (0.5 mm) = 5.4 x 10-2 W / 
Example: L = 1000 mm, W = 1 mm
 Rwire = R (L / W)
= (5.4 x 10-2 W /•
)(1000/1) = 54 W
EECS40, Fall 2004
Lecture 25a, Slide 5
Prof. White
Wire Capacitance: The Parallel Plate Model
single wire over
a substrate:
electric field lines
tdi
Relative Permittivities
C pp 
EECS40, Fall 2004
 di
t di
WL
Lecture 25a, Slide 6
Prof. White
Parallel-Plate Capacitance Example
• Oxide layer is typically ~500 nm thick
• Interconnect wire width is typically ~0.5 mm wide (1st level)
 capacitance per unit length = 345 fF/cm = 34.5 aF/mm
Example: L = 30 mm
 Cpp  1 fF (compare with Cn~ 2 fF)
EECS40, Fall 2004
Lecture 25a, Slide 7
Prof. White
Fringing-Field Capacitance
For W / tdi < 1.5, Cfringe is dominant
Wire capacitance per unit length:
cwire
w di
2di
 c pp  c fringe 

t di
log( t di / H )
EECS40, Fall 2004
Lecture 25a, Slide 8
H
w W 
2
Prof. White
Modeling an Interconnect
Problem: Wire resistance and capacitance to underlying
substrate is spread along the length of the wire
“Distributed RC line”
We will start with a simple model…
EECS40, Fall 2004
Lecture 25a, Slide 9
Prof. White
Lumped RC Model
Model the wire as single capacitor and single resistor:
• Cwire is placed at the end of the interconnect
 adds to the gate capacitance of the load
• Rwire is placed at the logic-gate output node
 adds to the MOSFET equivalent resistance
Rwire
Cwire
substrate
EECS40, Fall 2004
Lecture 25a, Slide 10
Prof. White
Cascaded CMOS Inverters w/ Interconnect
Equivalent resistance Rdr
Vin
(rwire, cwire, L)
Cintrinsic
Cfanout
Using “lumped RC” model for interconnect:
Rdr
Rwire
Cintrinsic
Cwire
Cfanout
 D  RdrCintrinsic  ( Rdr  Rwire )Cwire  C fanout 
 RdrCintrinsic  ( Rdr  Rwire )C fanout  ( Rdr  Rwire )Cwire
EECS40, Fall 2004
Lecture 25a, Slide 11
Prof. White
Effect of Interconnect Scaling
2di L 
 L    di
2


RwireCwire   
WL



L
di



log( tdi / H ) 
 WH   tdi
• Interconnect delay scales as square of L
 minimize interconnect length!
• If W is large, then it does not appear in RwireCwire
• Capacitance due to fringing fields becomes more significant
as W is reduced; Cwire doesn’t actually scale with W for small W
EECS40, Fall 2004
Lecture 25a, Slide 12
Prof. White
Propagation Delay with Interconnect
Using the lumped-RC interconnect model:
t p  0.69 D
 0.69 Rdr Cintrinsic  0.69( Rdr  Rwire )C fanout
 0.69( Rdr  Rwire )Cwire
In reality, the interconnect resistance & capacitance are
distributed along the length of the interconnect.
 The interconnect delay is actually less than RwireCwire:
t p  0.69 Rdr Cintrinsic  0.69( Rdr  Rwire )C fanout
 (0.69 Rdr  0.38Rwire )Cwire
The 0.38 factor accounts for the fact that the wire
resistance and capacitance are distributed.
EECS40, Fall 2004
Lecture 25a, Slide 13
Prof. White
Interconnect Wire-to-Wire Capacitance
A
B
C
oxide
Si substrate
Wire A simply has capacitance (Cpp + Cfringe) to substrate
Wire B has additional sidewall capacitance to neighboring wires
Wire C has additional capacitance to the wire above it
EECS40, Fall 2004
Lecture 25a, Slide 14
Prof. White
Wiring Examples - Intel Processes
Advanced processes: narrow linewidths, taller wires, close
spacing  relatively large inter-wire capacitances
k=3.6
Tungsten
Plugs
Tungsten
Plugs
Intel 0.25µm Process (Al)
5 Layers - Tungsten Vias
Source: Intel Technical Journal 3Q98
Intel 0.13µm Process (Cu)
Source: Intel Technical Journal 2Q02
EECS40, Fall 2004
Lecture 25a, Slide 15
Prof. White
Effects of Inter-Wire Capacitance
•
Capacitance between closely spaced lines
leads to two major effects:
1. Increased capacitive loading on driven nodes
(speed loss)
2. Unwanted transfer of signals from one place to
another through capacitive coupling
“crosstalk”
•
We will use a very simple model to estimate the
magnitude of these effects. In real circuit
designs, very careful analysis is necessary.
EECS40, Fall 2004
Lecture 25a, Slide 16
Prof. White
Approaches to Reducing Crosstalk
1. Increase inter-wire spacing (decrease CC)
2. Decrease field-oxide thickness (decrease CC/C2)
…but this loads the driven nodes and thus decreases circuit speed.
3. Place ground lines (or VDD lines) between signal lines
ground
SiO 2
Silicon substrate
EECS40, Fall 2004
Lecture 25a, Slide 17
Prof. White
Transistor Scaling
Average minimum L of MOSFETs vs. time
• Steady advances in
manufacturing technology
(particularly lithography)
have allowed for a steady
reduction in transistor size.
~13% reduction/year
(0.5 every 4-6 years)
• How should transistor
dimensions and supply
voltage (VDD) scale
together?
EECS40, Fall 2004
Lecture 25a, Slide 18
Prof. White
Scenario #1: Constant-Field Scaling
• Voltages and MOSFET dimensions are scaled
by the same factor S >1, so that the electric
field remains unchanged
xj
VDD
tox / S
xj / S
VDD / S
L/S
Doping NA
EECS40, Fall 2004
NA  S
Lecture 25a, Slide 19
Prof. White
Impact of Constant-Field Scaling
(a) MOSFET gate capacitance:

 L  W    ox
  LW Cox      
C gate
 S  S   tox
 S

 C gate

S


(b) MOSFET drive current:
2
W 

 VDD VT 
W  
I DSAT
2


S







 
I DSAT  Cox
VDD VT  SCox 

L  S 
L
S
 S
(c) Intrinsic gate delay :
 VDD


Cgate
Cgate / S VDD / S   CgateVDD  1
 

 

I DSAT / S 
I DSAT
 I DSAT  S
 Circuit speed improves by S
EECS40, Fall 2004
Lecture 25a, Slide 20
Prof. White
Impact of Constant-Field Scaling (cont’d)
(d) Device density:
area required per transistor  W L
1
1
S2
# of transistors per unit area 


W L W / S L / S  WL
(e) Power dissipated per device:

Ppeak
 I DSAT   VDD  Ppeak
 VDD
 
 I DSAT

 2
 S   S  S
(f) Power density:
Ppeak 
 Ppeak
1
1
 
 
Ppeak
 2  
W L S  W / S L / S   WL
 Power consumed per function is reduced by S2
EECS40, Fall 2004
Lecture 25a, Slide 21
Prof. White
VT Scaling?
• Low VT is desirable for high ON current:
1<<2
IDSAT  (VDD - VT)
• But high VT is needed for low OFF current:
log IDS
High VT
IOFF,low VT
0
EECS40, Fall 2004
Low VT
VT cannot be
aggressively
scaled down!
IOFF,high VT
VGS
VDD
Lecture 25a, Slide 22
Prof. White
• Since VT cannot be scaled down aggressively,
the power-supply voltage (VDD) has not been
scaled down in proportion to the MOSFET
channel length:
EECS40, Fall 2004
Lecture 25a, Slide 23
Prof. White
Scenario #2: Generalized Scaling
• MOSFET dimensions are scaled by a factor S >1;
Voltages (VDD & VT) are scaled by a factor U >1
L = L / S ; W = W / S ; tox = tox / S
VDD = VDD / U
Note: U is slightly smaller than S
(a) MOSFET drive current:
2
W 


SI DSAT
W
 VDD  VT 
2


S








I DSAT  Cox
VDD  VT  SCox 

 

L
L
U2
 U 
 S
(b) Intrinsic gate delay:
 VDD


Cgate
Cgate / S VDD / U   CgateVDD  U
  2

 
2

I DSAT
SI DSAT / U
 I DSAT  S

EECS40, Fall 2004

Lecture 25a, Slide 24
Prof. White
Impact of Generalized Scaling
(c) Power dissipated per device:

Ppeak
 SI DSAT   VDD  SPpeak
 VDD
 
 I DSAT


2  
3
 U   U  U
(d) Power dissipated per unit area:
SPpeak 
 S 3 Ppeak Ppeak
1
1
 
  3
Ppeak
 3  

W L U  W / S L / S   U WL WL
• Reliability (due to high E-fields) and power density are issues!
EECS40, Fall 2004
Lecture 25a, Slide 25
Prof. White
Intrinsic Gate Delay (CgateVDD / IDSAT)
0.85V
VDD=0.75V
EECS40, Fall 2004
Lecture 25a, Slide 26
Prof. White
Silicon-on-Insulator (SOI) Technology
TSOI
• Transistors are fabricated in a thin single-crystal Si layer
on top of an electrically insulating layer of SiO2




Simpler device isolation  savings in circuit layout area
Low pn-junction & wire capacitances  faster circuit operation
No “body effect”
Higher cost
EECS40, Fall 2004
Lecture 25a, Slide 27
Prof. White
Global Interconnects
• For global interconnects (long wires used to route VDD,
GND, and voltage signals across a chip), the wire resistance
dominates the resistance of the driving logic gate
(i.e. Rwire >> Rdr)
 RwireCwire  L2
• The length of the longest wires on a chip increases slightly
(~20%) with each new technology generation. In order to
minimize increases in global interconnect delay, the crosssectional area of global interconnects has not been scaled,
i.e. W and H are not scaled down for global interconnects
=> Place global interconnects in separate planes of wiring
EECS40, Fall 2004
Lecture 25a, Slide 28
Prof. White
Interconnect Technology Trends
• Reduce the inter-layer dielectric permittivity
– “low-k” dielectrics (r  2)
• Use more layers of wiring
− average wire length is reduced
− chip area is reduced
wire delay
increases
gate delay
Intel 0.13µm Process (Cu)
Source: Intel Technical Journal 2Q02
EECS40, Fall 2004
Lecture 25a, Slide 29
Prof. White