Transcript lec3-dic

Manufacturing
Process
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Introduction
What is a Semiconductor?
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Low resistivity => “conductor”
High resistivity => “insulator”
Intermediate resistivity => “semiconductor”
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conductivity lies between that of conductors and insulators
generally crystalline in structure for IC devices
 In recent years, however, non-crystalline semiconductors
have become commercially very important
polycrystalline amorphous crystalline
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Semiconductor Materials
Phosphorus
(P)
Galliu
m
(Ga)
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Silicon
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Si has four valence electrons. Therefore, it can form
covalent bonds with four of its nearest neighbors.
When temperature goes up, electrons can become
free to move about the Si lattice.
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Doping (N type)
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Si can be “doped” with other elements to change its
electrical properties.
For example, if Si is doped with phosphorus (P),
each P atom can contribute a conduction electron,
so that the Si lattice has more electrons than holes,
i.e. it becomes “N type”:
Notation:
n = conduction electron
concentration
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Doping (P type)
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If Si is doped with Boron (B), each B atom can
contribute a hole, so that the Si lattice has more
holes than electrons, i.e. it becomes “P type”:
Notation:
p = hole concentration
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CMOS Process
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A Modern CMOS Process
gate-oxide
TiSi2
AlCu
SiO2
Tungsten
poly
p-well
n+
SiO2
n-well
p+
p-epi
p+
Dual-Well Trench-Isolated CMOS Process
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Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
Vout2
M3
M1
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Its Layout View
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The Manufacturing Process
For a great tour through the IC manufacturing process
and its different steps, check
http://www.fullman.com/semiconductors/semiconductors.html
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Patterning of SiO2
Chemical or plasma
etch
Si-substrate
Hardened resist
SiO
2
(a) Silicon base material
Si-substrate
Photoresist
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
Si-substrate
Hardened resist
SiO
2
(b) After oxidation and deposition
of negative photoresist
Si-substrate
UV-light
Patterned
optical mask
(e) After etching
Exposed resist
SiO
2
Si-substrate
Si-substrate
(f) Final result after removal of resist
(c) Stepper exposure
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Photo-Lithographic Process
optical
mask
oxidation
photoresist
removal (ashing)
photoresist coating
stepper exposure
Typical operations in a single
photolithographic cycle (from [Fullman]).
photoresist
development
acid etch
process
step
spin, rinse, dry
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CMOS Process at a Glance
Define active areas
Etch and fill trenches
Implant well regions
Deposit and pattern
polysilicon layer
Implant source and drain
regions and substrate contacts
Create contact and via windows
Deposit and pattern metal layers
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CMOS Process Walk-Through
p-epi
(a) Base material: p+ substrate
with p-epi layer
p+
SiN
34
SiO
2
p-epi
(b) After deposition of gate-oxide and
sacrificial nitride (acts as a
buffer layer)
p+
(c) After plasma etch of insulating
trenches using the inverse of
the active area mask
p+
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CMOS Process Walk-Through
SiO
2
(d) After trench filling, CMP
planarization, and removal of
sacrificial nitride
n
(e) After n-well and
V
adjust implants
Tp
p
(f) After p-well and
V
adjust implants
Tn
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CMOS Process Walk-Through
poly(silicon)
(g) After polysilicon deposition
and etch
n+
p+
(h) After n+ source/drain and
p+source/drain implants. These
steps also dope the polysilicon.
SiO
2
(i) After deposition of SiO
insulator and contact hole2etch.
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CMOS Process Walk-Through
Al
(j) After deposition and
patterning of first Al layer.
Al
SiO
2
(k) After deposition of SiO
insulator, etching of via’s, 2
deposition and patterning of
second layer of Al.
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Advanced Metallization
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Advanced Metallization
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Implantation
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Diffusion implantation:
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Ion implantation:
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The wafers are placed in a quartz tube embedded in a heated
furnace.
A gas containing the dopant is introduced in the tube. The high
temperatures of the furnace, typically 900 to 1100 °C, cause the
dopants to diffuse into the exposed surface both vertically and
horizontally.
Dopants are introduced as ions into the material.
The ion implantation system directs and sweeps a beam of purified
ions over the semiconductor surface.
The acceleration of the ions determines how deep they will
penetrate the material, while the beam current and the exposure
time determine the dosage.
The ion implantation method allows for an independent control of
depth and dosage.
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Deposition
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Oxidation:
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Chemical vapor deposition (CVD):
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The wafer is exposed to a mixture of high-purity oxygen
and hydrogen at approximately 1000°C.
The oxide is used as an insulation layer and also forms
transistor gates.
CVD uses a gas-phase reaction with energy supplied by
heat at around 850°C.
silicon nitride (Si3N4) ,Polysilicon,
Sputtering:
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The aluminum is evaporated in a vacuum, with the heat for
the evaporation delivered by electron-beam or ion-beam
bombarding.
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Etching
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Wet etching:
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It uses many types of acid, base and caustic solutions to remove a
material.
For instance, hydrofluoric acid buffered with ammonium fluoride is
typically used to etch SiO2.
Dry or plasma etching:
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A wafer is placed into the etch tool's processing chamber and given
a negative electrical charge.
The chamber is heated to 100°C and brought to a vacuum level of
7.5 Pa,
It then filled with a positively charged plasma (usually a mix of
nitrogen, chlorine and boron trichloride).
The opposing electrical charges cause the rapidly moving plasma
molecules to align themselves in a vertical direction, forming a
microscopic chemical and physical “sandblasting” action which
removes the exposed material.
It creates patterns with sharp vertical contours.
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