Transcript The Evolution of RISC A Three Party Rivalry

The Evolution of RISC
A Three Party Rivalry
By Jenny Mitchell
CS147 Fall 2003 Dr. Lee
Tradition
• Registers increased complexity of wiring to
CPU, memory was simpler (and faster)
• GOAL: Provide every addressing mode for
every instruction.
• Complex, but would be individually tuned
for fast results for a programmer
Tradition
• In late 1970s, determined most addressing
modes being ignored because of compiler
design
• CPUs started to run faster than memory
• Wanted to streamline processing within the
CPU while reducing memory access
Half Time
• Ideas? Pipelining; running in parallel
• This added complexity to CPU -- space is
limited!
The Next Level
• Solution = design a CPU with more
registers and fewer instructions
• Andrew Tanenbaum
– Noticed most constants would fit in 13 bits, but
16 or 32 were allocated
– Could be stored in leftover bits if instructions
were small enough
The Next Level --> RISC
• Reduced Instruction Set Computing
– Slightly smaller set of instructions
– Allows everything to be accomplished in registers -Load & Store architecture
• Chip has fewer transistors dedicated to core logic
– Increase size of register set
– Increase internal parallel implementation
– Add SIMD processors
• Design is simpler = costs are lower
The Three Major Teams
IBM
• Research project led by Robert Cooke in
1975
• IBM 801 CPU completed in 1977
• Powered I/O for IBM mainframes
• Never commercialized
• Eventually became the PowerPC chip
architecture used by Motorola & Apple
The Three Major Teams
U.C. Berkeley
• Project founded by David Patterson in 1980
• Gained performance through pipelining and
register windowing
– Requiring max 8 registers, changed pointer to a
different set of 8
• RISC-I in 1982 consisted of 44,420 transistors
• RISC-II used by Sun Microsystems to produce
SPARC, took over workstation market
Berkeley RISC
From University of Teeside website
The Three Major Teams
Stanford
• John Hennessy started MIPS project in
1981
• Each instruction ran & completed in a
single clock cycle
• Used code reordering, branch prediction,
and superpipelining to increase performance
• Commercialized into MIPS Technologies,
Inc. - most populous chip found in all
Nintendo systems
Stanford MIPS
From Stanford website
Next Generation
PowerPC
• Apple, IBM, & Motorola formed alliance in
1990 to fit all their needs
• Superscalar, dispatched over three units
– Branch
– Fixed-point arithmetic
– Floating-point units
Next Generation
PowerPC
From Stanford website
Next Generation
PowerPC
• Branching implemented by 8 conditional
registers which are set by a bit of the
opcode
• Complete 64 bit specification
– PowerPC 601 was first released in 1994
– PowerPC 604 was 32bit architecture
– PowerPC 620 was 64bit architecture
Next Generation
PowerPC 970
• IBM PPC 970 introduced late 2002, now
shipping in Apple computers
• 64 bit microprocessors with native 32 bit
compatibility (not simulated)
• 64 bit effective / 42 bit real addressing
• 8 instructions fetch/cycle
The Next Generation
PowerPC 970
From IBM website
The Next Generation
Others?
• Intel lagged behind because of continued
backwards compatibility for x86 architecture
• Intel Itanium has 221 million transistors using 130
watts of power - equivalently, could have 4 IBM
POWER chips on single processor
• AMD split from Intel with its native 64 bit
processor not compatible with IA 64 system
– AMD64 Opteron in early 2003 runs mainly for servers
and workstations
BUY APPLE!
(just joking….a little…)
References
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www.apple.com
www.BYTE.com
www.ibm.com
www.nationmaster.com/encyclopedia/
www.stanford.edu