Multilevel Machines Level 0
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Transcript Multilevel Machines Level 0
Structured Computer Organization
• A large gap between what is convenient for people and
what is convenient for computers
• Solutions
– Translation – entire program is translated into
new language before being executed.
– Interpretation – each instruction is examined
and decoded, and then executed.
• Can create abstraction using virtual machines, each
with it’s own machine language
• Languages should not be too different
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Virtual Machine Levels 0 through 5
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Multilevel Machines
• Level 0 – Digital Logic Level
– Gate level, made from transistors, used to form 1-bit
memories. Memories combined to form 16,32, or 64bit registers. (could actually go lower)
Level 1 – Microarchitecture Level
– Collection of 8-32 registers that form a local memory
and a circuit called an ALU (Arithmetic Logic Unit).
Registers and ALU connected to form a data path.
Data path may be controlled by software or hardware.
Does fetching, examining, and executing of
instructions, either through an interpreter or hardwired
control.
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Multilevel Machines
• Level 2 – Instruction Set Architecture
– The instructions that are carried out
interpretively by the underlying levels.
Everything lower is proprietary.
• Level 3 – Operating System Machine Level
– A new set of instructions (as well as those from
level 2), a different memory organization, the
ability to run 2 or more programs concurrently,
various other features. Hybrid level.
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Multilevel Machines
• Level 4 – Assembly Language Level
– Finally have words and abbreviations rahter
than just numbers. A symbolic form for one of
the underlying languages.
• Level 5 – High-level Language Level
– Languages designed to used by applications
programmers.
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The Intel CPU Family
Chip
Date
MHz
4004
4/1971
0.108
8008
4/1972
0.108
8080
4/1974
2-3
8085
4/1976
3-8
8086
6/1978
5-10
8088
6/1979
5-8
80286
2/1982
8-12
80386
10/1985
16-33
80486
4/1989 25-100
Pentium
3/1993 60-233
Pentium Pro 3/1995 150-200
Pentium II
5/1997 233-400
Pentium III
1998
550
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Transistors Memory
2,300
3,500
6,000
6,500
29,000
29,000
134,000
275,000
1.2M
3.1M
5.5M
7.5M
9.5M
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Notes
640 First microprocessor on a chip
16KB First 8-bit processor
64KB First general-purpose CPU on a chip
64KB
1MB First 16-bit CPU on a chip
1MB Used in IBM PC
16MB Memory protection present
4GB First 32-bit CPU
4GB Built-in 8K cache memory
4GB Two pipelines; later models had MMX
4GB Two levels of cache built in
4GB Pentium Pro plus MMX
Streaming SIMD extensions (SSE)
The Original Von Neumann
Machine
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Block Diagram for a Simple Computer
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Internal Block Diagram of a CPU
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Pipelining
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Registers of the 8086/80286 by Category
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