Transcript Switch-Level Modeling

Switch-Level Modeling
How to describe a switch-level
circuit ?
Verilog Switch Primitives
Modeling transistor networks at the switch-level more
accurately represents their operation.
Verilog provides unidirectional and bidirectional primitives
that you can use to model the switch networks:
• The following are unidirectional primitives:
cmos nmos pmos pullup
rcmos rnmos rpmos pulldown
• The following are bidirectional primitives:
tran
rtran
tranif0
rtranif0
tranif1
rtranif1
Switch Instantiation
Gate
Source
Drain
nmos(drain,source,gate);
Switch Instantiation
Gate
Source
Drain
pmos(drain,source,gate);
Switch Instantiation
Gate
Source
Drain
nmos(drain,source,gate);
Switch Instantiation
pgate
Source
Drain
ngate
cmos (drain, source, ngate, pgate)
Switch Instantiation
data1
data2
control
tranif0 (data1, data2, control);
tranif1 (data1, data2, control);
Switch Delay
You can assign delays to some switch types:
 The unidirectional coms,nmos,and pmos switches can have rise,fall,and turn-off
delays
coms #(<delay>) (d, s, ng, pg);
nmos #(<rise_delay>,<fall_delay>) (d, s, g);
pmos #(<rise_delay>,<fall_delay>),<turnoff_delay>) (d, s, g);
 The bidirectional switches tranif0 and tranif1 can have turn-on and turn-off
delays,but no source-drain channel delays
tranif0 #(<delay>) (d, s, g);
tranif1 #(<turnon_delay>,<turnoff_delay>) (d, s, g);
 The pulldown,pullup,and tran gates cannot have delays
Note: You can specify delays in min:typ:max format.
Drive Strength
You can assign strengths to some primitive types:
 The pulldown and pullup primitives can have one or two drive strengths



the simulator ignores the unneeded strength specification
pullup (weak1, weak0) (net1);
The boolean primitives can have two drive strengths
You must specify both drive strengths,or none
nand (highz1, strong) (net1,net2,net3);
The trireg net type can have charge strengths
trireg (small) net1;
The switch primitives CANNOT have drive strengths!
Level
7
6
Drive
supply strong
Charge
5
pull
4
large
3
weak
2
medium
1
small
0
highz
Strength Reduction
The switches can reduce the strength of signals passing through them:


The cmos,nmos,pmos,tran,tranif0,and tranif1 primitives reduce a
supply strength signal to a strong signal
The rcmos,rnmos,rpmos,rtran,rtranif0,and rtranif1 primitives reduce
signal strength according to the following table:
Input strength Reducel strengh
7 – supply
6 – strong
5 – pull
4 – large
3 – weak
2 – medium
1 – small
0 – highz
5 – pull
5 – pull
3 – weak
2 – medium
2 – medium
1 – small
1 – small
0 – highz
Switch-Level Networks
Switch networks may contain unidirectional and bidirectional switches.
Verilog-XL partitions switch-level networks into channel-connected regions.
The Switch-XL Algorithm
Use the Switch-XL algorithm to:
 Accelerate simulation of bidirectional switches


--- The XL algorithm does not accelerate bidirectional switches
Simulate up to 250 relative drive strengths on switches
Simulate up to 250 relative charge strengths on trireg nets
s1
s2
2
1
s3
Transistor
Strengths
1
Selecting the Switch-XL Algorithm
Use the +switchxl option to globally enable the Switch-XL algorithm.
verilog source.v +switchxl
Use the `switch compiler directive to selectively enable the Switch-XL algorithm.
`switch XL
// control networks here
`switch default
// datapath networks here
Use the Switch-XL algorithm:
---For a significantly –sized network of bidirectional switches
---For a network of switches you cannot otherwise correctly functionally model with
only 2 switch drive strengths and 4 (including none)net charge strengths
Use the default algorithm:
---For a network of densely-packed significantly-sized regularly-structured
pass transistors
The Switch-XL Strength Model
The drive strength expression must evaluate to a number from 1 to 250.
These statements declare tran switches and assign relative drive strengths.
Switch t1 has the largest conductance relative to t0 and rt.
tranif1 strength(3) t1 (s0,d0,g0);
tranif0 strength(2) t0 (s1,d1,g1);
rtran strength(1) rt (s2,d2);
The charge strength expression must evaluate to a number from 0 to 250.
These statements declare trireg nets and assign relative charge strengths.
Net a has the largest capacitance relative to b,c and d.
trireg strength(25) a;
trireg strength(10) b;
trireg strength(5) c;
trireg strength(1) d;
Switch-XL Strength Reduction
The Switch-XL and default algorithms reduce signal strength differently:
 The default algorithm:

--- Reduces signal strength by 0,1,or 2 levels for each switch instance
--- An rtran reduces a weak drive to a medium charge
The Switch-XL algorithm:
--- Treats all drive strengths as higher than charge strengths
--- Maps standard strengths into the range of network strengths
--- Reduces strength once (by the highest resistance) in the channel
pullup
Default
Switch-Xl
pulldown
Pu1 We1 Me1 Me0 We0 Pu0
StX StX StX StX StX StX
pullup
Default
Switch-Xl
(same channel)
pulldown
Pu1 We1 Me1
St1 St1 St1
Me0 We0 Pu0
St0 St0 St0
How Switch-XL Works
The Switch-XL algorithm performs the following steps:
1. Detects channel-connected switch networks containing at least one
bidirectional switch
2. Converts the timing model of unidirectional switches in these networks from the
rise/fall/turn-off model to the turn-on/turn-off model of bidirectional switches
3. Optimizes these networks,including removing nets
4. Compiles these networks into accelerative expressions for the XL engine
vdd
y
a
n1
b
vss
Switch-XL can remove net n1
Timing Model Conversion
In channel-connected regions containing at least one bidirectional switch,
Switch-XL converts the unidirectional switch timing model to the bidirectional
switch timing model,so that it can accelerate the region:


It converts rise/fall delays into turn-on/turn-off delays
--- The rise delay becomes the turn-on delays,fall becomes turn-off
It converts rise/fall/turn-off delays into turn-on/turn-off delays
--- The smaller of the rise and fall delays becomes the turn-on delay
nmos
nmos
nmos
nmos
tranif1
not converted
nmos
tranif1
nmos
nmos
timing model converted
Summary
In this section, you learned about:
 Switch-level modeling
 The Switch-XL algorithm
 Choose an acceleration algorithm
Review
1. Name the Verilog bidirectional primitives.
2. How do the delay models for the unidirectional and
bidirectional switches differ?
3. A Verilog-XL switch-level network contains which
types of switches?
4. What is the range of charge strengths you can assign
to a Switch-XL trireg net?
5. How does Switch-XL reduce signal strength in channel?