Transcript Lecture 20 ppt

Lecture 20
Caches and Virtual Memory
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Memories: Review
•
SRAM:
– value is stored on a pair of inverting gates
– very fast but takes up more space than DRAM (4 to 6 transistors)
•
DRAM:
– value is stored as a charge on capacitor (must be refreshed)
– very small but slower than SRAM (factor of 5 to 10)
Word line
A
A
B
B
Pass transistor
Capacitor
Bit line
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Exploiting Memory Hierarchy
•
Users want large and fast memories!
SRAM
DRAM
Disk
•
.5 – 5ns
$4000 to $10,000 per GB.
50-70ns
$100 to $200 per GB.
5 to 20 million ns $.50 to $2 per GB.
Build a memory hierarchy
2004
CPU
Level 1
Increasing distance
from the CPU in
access time
Levels in the
Level 2
memory hierarchy
Level n
Size of the memory at each level
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Locality
•
A principle that makes having a memory hierarchy a good idea
•
If an item is referenced,
temporal locality: it will tend to be referenced again soon
spatial locality: nearby items will tend to be referenced soon.
Why does code have locality?
•
Our initial focus: two levels (upper, lower)
– block: minimum unit of data
– hit: data requested is in the upper level
– miss: data requested is not in the upper level
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Cache
•
•
Two issues:
– How do we know if a data item is in the cache?
– If it is, how do we find it?
Our first example:
– block size is one word of data
– "direct mapped"
For each item of data at the lower level,
there is exactly one location in the cache where it might be.
e.g., lots of items at the lower level share locations in the upper level
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Direct Mapped Cache
•
Mapping: address is modulo the number of blocks in the cache
000
001
010
011
100
101
110
111
Cache
00001
00101
01001
01101
10001
10101
11001
11101
Memory
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Direct Mapped Cache
Address (showing bit positions)
•
31 30
For MIPS:
Hit
13 12 11
20
2 10
Byte
offset
10
Tag
Data
Index
Index
0
1
2
Valid Tag
Data
1021
1022
1023
20
32
=
What kind of locality are we taking advantage of?
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Direct Mapped Cache
•
Taking advantage of spatial locality:
Address (showing bit positions)
31
14 13
18
Hit
65
8
210
4
Tag
Byte
offset
Data
Block offset
Index
18 bits
V
512 bits
Tag
Data
256
entries
16
32
32
32
=
Mux
32
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Hits vs. Misses
•
Read hits
– this is what we want!
•
Read misses
– stall the CPU, fetch block from memory, deliver to cache, restart
•
Write hits:
– can replace data in cache and memory (write-through)
– write the data only into the cache (write-back the cache later)
•
Write misses:
– read the entire block into the cache, then write the word
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Performance
•
Increasing the block size tends to decrease miss rate:
40%
35%
Miss rate
30%
25%
20%
15%
10%
5%
0%
4
16
64
Block size (bytes)
256
1 KB
8 KB
16 KB
64 KB
256 KB
•
Use split caches because there is more spatial locality in code:
Program
gcc
spice
Lecture 20 – Caching and Virtual Memory
Block size in
words
1
4
1
4
Instruction
miss rate
6.1%
2.0%
1.2%
0.3%
Data miss
rate
2.1%
1.7%
1.3%
0.6%
2004 Morgan Kaufmann Publishers
Effective combined
miss rate
5.4%
1.9%
1.2%
0.4%
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Performance
•
Simplified model:
execution time = (execution cycles + stall cycles)  cycle time
stall cycles = # of instructions  miss ratio  miss penalty
•
Two ways of improving performance:
– decreasing the miss ratio
– decreasing the miss penalty
What happens if we increase block size?
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Virtual Memory
•
Main memory can act as a cache for the secondary storage (disk)
Virtual addresses
Physical addresses
Address translation
Disk addresses
•
Advantages:
– illusion of having more physical memory
– program relocation
– protection
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Pages: virtual memory blocks
•
Page faults: the data is not in memory, retrieve it from disk
– huge miss penalty, thus pages should be fairly large (e.g., 4KB)
– reducing page faults is important (LRU is worth the price)
– can handle the faults in software instead of hardware
– using write-through is too expensive so we use writeback
Virtual address
31 30 29 28 27
15 14 13 12 11 10 9 8
3210
Page offset
Virtual page number
Translation
29 28 27
15 14 13 12 11 10 9 8
Physical page number
3210
Page offset
Physical address
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Page Tables
Virtual page
number
Page table
Physical page or
Valid disk address
1
1
1
1
0
1
1
0
1
1
0
1
Lecture 20 – Caching and Virtual Memory
Physical memory
Disk storage
2004 Morgan Kaufmann Publishers
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Page Tables
Page table register
Virtual address
31 30 29 28 27
1 5 1 4 1 3 1 2 11 1 0 9 8
Virtual page number
Page offset
12
20
Valid
3 2 1 0
Physical page number
Page table
18
If 0 then page is not
present in memory
29 28 27
1 5 1 4 1 3 1 2 11 1 0 9 8
Physical page number
3 2 1 0
Page offset
Physical address
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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Making Address Translation Fast
•
A cache for address translations: translation lookaside buffer
TLB
Virtual page
number Valid Dirty Ref
1
1
1
1
0
1
0
1
1
0
0
0
Physical page
address
Tag
1
1
1
1
0
1
Physical memory
Page table
Physical page
Valid Dirty Ref or disk address
1
1
1
1
0
1
1
0
1
1
0
1
Typical values:
Lecture 20 – Caching and Virtual Memory
1
0
0
0
0
0
0
0
1
1
0
1
1
0
0
1
0
1
1
0
1
1
0
1
Disk storage
16-512 entries,
miss-rate: .01% - 1%
miss-penalty: 10 – 100 cycles
2004 Morgan Kaufmann Publishers
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TLBs and Caches
Virtual address
31 30 29
14 13 12 11 10 9
Virtual page number
3 2 1 0
Page offset
12
20
Valid Dirty
Tag
Physical page number
=
=
=
=
=
=
TLB
TLB hit
20
Page offset
Physical page number
Physical address
Block
Cache index
Physical address tag
offset
18
8
4
Byte
offset
2
8
12
Valid
Data
Tag
Cache
=
Cache hit
32
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
Data
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Further steps
• Read the rest of the book
• Take Computer Architecture
• Take Operating Systems
Lecture 20 – Caching and Virtual Memory
2004 Morgan Kaufmann Publishers
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