Transcript Microprocessors

Memory Devices and Interfacing – (Chapter 9)
Dr. Costas Kyriacou and Dr. Konstantinos Tatas
Outline
• Semiconductor Memory Basic Concepts
• Read Only Memory (ROM)
• Random Access Memory (RAM)
– SRAM
– DRAM
• Memory Interfacing
– Address size expansion
– Word size expansion
• Timing Analysis
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Basic Concepts
• A memory device can be viewed as a
single column table.
– Table index (row number) refers to
the address of the memory.
– Table entries refer to the memory
contents or data.
– Each table entry is referred as a
memory location or as a word.
• Both the memory address and the
memory contents are binary numbers,
expressed in most cases in Hex format.
• The size of a memory device is
specified as the number of memory
locations X width or word size (in bits).
– For example a 1K X 8 memory
device has 1024 memory locations,
with a width of 8 bits.
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Memory Address
Binary
Hex
Memory
Contents
00-0000-0000
000
10011001
00-0000-0001
00-0000-0010
001
002
00111000
11001001
00-0000-0011
003
00111011
11-1111-1100
3FC
01101000
11-1111-1101
11-1111-1110
3FD
3FE
10111001
00110100
11-1111-1111
3FF
00011000
1024 X 8 (or 1KX8) Memory
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Address Lines
• A memory device or memory chip must have
three types of lines or connections: Address,
Data, and Control.
• Address Lines: The input lines that select a
memory location within the memory device.
– Decoders are used, inside the memory chip, to
select a specific location
– The number of address pins on a memory chip
specifies the number of memory locations.
• If a memory chip has 13 address pins
(A0..A12), then it has:
213 = 23 X 210 = 8K locations.
• If a memory chip has 4K locations, then it
should have N pins:
A00
A01
An-2
An-1
Y00
Y01
Y02
Y03
Location 000
Location 001
Location 002
Location 003
YFC
YFD
YFE
YFF
Location 0FC
Location 0FD
Location 0FE
Location 0FF
2N = 4K = 22 X 210 = 212  N=12 address
pins (A0..A11)
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Data Lines
• Data Connections: All memory devices have a set of data output pins (for ROM
devices), or input/output pins (for RAM devices).
– Most RAM chips have common bi-directional I/O connections.
– Most memory devices have 1, 8 or 16 data lines.
Data Input Lines
(DI0..DIn-1)
k- address lines
(A0..A m-1 )
Read (RD)
Write (WR)
2m words
n-bits per
word
k- address lines
(A0..Am-1 )
2m words
k- address lines
(A0..A m-1 )
2m words
Read/Write (R/W)
Chip Select (CS)
n-bits per
word
Output Enable (OE)
Chip Select (CS)
n-bits per
word
Chip Select (CS)
Data Output Lines
(DO0..DOn-1 )
(2m X n) RAM with separate I/P
and O/P Data lines
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Data Input/Output
Lines (D0..Dn-1 )
(2m X n) RAM with common I/P
and O/P Data lines
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Data Output Lines
(D0..Dn-1 )
(2m X n) ROM with only O/P Data
lines
5
Control Lines
• Enable Connections:
– All memory devices have at least one Chip Select (CS) or Chip Enable (CE)
input, used to select or enable the memory device.
• If a device is not selected or enabled then no data can be read from, or
written into it.
• The CS or CE input is usually controlled by the microprocessor through the
higher address lines via an address decoding circuit.
• Control Connections:
– RAM chips have two control input signals that specify the type of memory
operation: the Read (RD) and the Write (WR) signals.
• Some RAM chips have a common Read/ Write (R/W) signal.
– ROM chips can perform only memory read operations, thus there is no need
for a Write (WR) signal.
• In most real ROM devices the Read signal is called the Output Enable
(OE) signal.
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Memory Read Operations
• A memory read operation is carried out in the following steps:
– The processor loads on the Address bus the address of the memory location to be read (Step 1).
• Some of the address lines select the memory devices that owns the memory location
to be read (Step 1a), while the rest point to the required memory location within the
memory device.
– The processor activates the Read (RD) signal (Step 2).
• The selected memory device loads on the data bus the content of the memory
location specified by the address bus (Step 3).
– The processor reads the data from the data bus, and resets the RD signal (Step 4).
Clock
T1
Address Bus
T2
T3
Valid Address
Chip Enable
Read (RD)
Data Bus
Invalid Data
Step 1a
Step 1
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Step 2
Valid Data
Step 3
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Step 4
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Memory Write Operations
• A memory write operation is carried out in the following steps:
– The processor loads on the Address bus the address of the memory location (Step 1).
• Some of the address lines select the memory devices that owns the memory location
to be written (Step 1a), while the rest point to the required memory location within
the memory device.
– The processor loads on the data bus the data to be written (Step 2).
– The processor activates the Write (WR) signal (Step 3).
• The data at the data bus is stored in the memory location specified by the address
bus (Step 4).
Clock
T1
T2
Address Bus
T3
Valid Address
Data Bus
Valid Data
Chip Enable
Write (WR)
Step 2
Step 1
Step 1a
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Step 3
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Step 4
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Types of Semiconductor Memory Devices
•
Read Only Memory (ROM)
A memory device that maintains its
data permanently (or until the device
is reprogrammed).
Random Access Memory (RAM)
• A memory device that can be read
and written.
–
– Non-volatile: It maintains its data
even without power supply.
•
Used to store
– Programs such as the BIOS.
– Data such as look tables
• e.g. the bit pattern of the
characters in a dot matrix
printer.
•
A ROM device can be
1. Masked ROM (Programmed by the
manufacturer)
2. Programmable ROM (can be
program-erased-reprogrammed
many times
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–
•
Used to store
–
–
•
Volatile: It looses its data when the
power supply is switched-off
When the supply is switched-on it
contains random data
User programs that are loaded
from a secondary memory (disk)
Temporary data used by programs
such as variables and arrays.
A RAM device can be
1. Static
2. dynamic
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A Read Only Memory Example
• Implementation of an 8X4 ROM using (a) a decoder and OR-gates and (b) a
decoder and diodes.
+5V
A0
A1
A2
CS
3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7
A0
A1
A2
CS
3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7
OE
OE
D3
D2
D1
D0
D3
D2
D1
D0
Address 000 001 010 011 100 101 110 111
Data
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0011 0010 0100 0011 1010 0000 0101 1000
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A Programmable Read Only Memory Example
• Implementation of an 8X4 ROM using a decoder and fused links.
+5V
A0
A1
A2
CS
3/8 DEC.
Y0
Y1
A0
Y2
A1
Y3
Y4
A2
Y5
Y6
E
Y7
OE
D3
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D2
D1
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D0
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Types of semiconductor memory devices: EPROM
• EPROM is a type of ROM that can be erased and re-programmed. There are two types
of EPROMs: the ultra-violet (UV-EPROMs) and the electrically erasable (EEPROMs)
often called the flash memory.
• UV-EPROMs are erased by inserting the device in ultra violet light and programmed
using a special EPROM programmer. UV-EPROMs need to be removed from the PCB
in order to erased and programmed.
• The most common family of EPROMs is the 27XXX series, or the CMOS 27CXXX
where XXX indicates the memory capacity in Kbits. Some members of this family are
the following:
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2716/27C16
(2Kx8)
2732/27C16
(4Kx8)
2764/27C64
(8Kx8)
27128/27C128
(16Kx8)
27256/27C256
(32Kx8)
27512/27C512
(64Kx8)
27010/27C010
(128Kx8)
271024/27C1024 (64Kx16)
27020/27C020
(256Kx8)
272048/27C2048 (128Kx16)
27040/27C040
(512Kx8)
274096/27C4096 (256Kx16)
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RAM Cells
Static RAM (SRAM):
• The basic element of a static RAM cell is the
D-Latch.
• Data remains stored in the cell until it is
intentionally modified.
• SRAM is fast (Access time: 1ns).
• SRAM needs more space on the
semiconductor chip than DRAM.
Dynamic RAM (DRAM):
• DRAM stores data in the form of electric
charges in capacitors.
• Charges leak out, thus need to refresh
data every few ms.
• DRAM is slow (Access time: 60ns).
• DRAM needs less space on the
semiconductor chip than SRAM.
– SRAM more expensive than DRAM
– SRAM needs more space than DRAM
– DRAM less expensive than SRAM
– DRAM needs less space than SRAM
• SRAM consumes power only when accessed. • DRAM needs to be refreshed
• DRAM is used as the main memory
• SRAM is used as a Cache
Bit Select
Bit Select
Data In
D
Q
Data Out
Data Out
Data In
Write
En
RAM Cell
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DRAM Cell
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Types of semiconductor memory devices: Static RAM
• Static RAM (also called SRAM)devices retain their data for as long as the DC power is
applied.
• The most common family of SRAM are the 61XXX, 62XXX or the CMOS 62CXXX
series, where XXX indicates the memory capacity in Kbits. Some members of this
family are the following:
6116/6216
(2Kx8)
6164/6264
(8Kx8)
61256/62256
(32Kx8)
611024/621024 (128Kx8)
• These series of SRAM devices are pin compatible with the 27XXX series of EPROMs,
with the difference that the WR signal is replaced by the programming voltage pin
(Vpp) on the EPROM. This allows a single socket on the PCB hold either a SRAM,
during system development, or an EPROM, after the operation of the program is
verified to be the expected one.
• Static RAM is fast with access times much less than 100ns. SRAM chips with access
times less than 10ns are often used as cache memory in computers.
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DYNAMIC RAM CELL ARRAY
• Asynchronous DRAM
• This is the basic form, from which all others are derived.
An asynchronous DRAM chip has power connections,
some number of address inputs (typically 12), and a few
(typically 1 or 4) bidirectional data lines. There are four
active low control signals:
• /RAS, the Row Address Strobe. The address inputs are
captured on the falling edge of /RAS, and select a row to
open. The row is held open as long as /RAS is low.
• /CAS, the Column Address Strobe. The address inputs are
captured on the falling edge of /CAS, and select a column
from the currently open row to read or write.
• /WE, Write Enable. This signal determines whether a
given falling edge of /CAS is a read (if high) or write (if
low). If low, the data inputs are also captured on the
falling edge of /CAS.
• /OE, Output Enable. This is an additional signal that
controls output to the data I/O pins. The data pins are
driven by the DRAM chip if /RAS and /CAS are low, and
/WE is high, and /OE is low. In many applications, /OE
can be permanently connected low (output always
enabled), but it can be useful when connecting multiple
memory chips in parallel.
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DRAM BLOCK DIAGRAM
• © Samsung Electronics
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DYNAMIC RAM
• DRAM requires refreshing every 2 to 4 ms .
• Refreshing occurs automatically during a read or write.
• Internal circuitry takes care of refreshing cells that are not accessed over this interval.
– For a 256K X 1 DRAM with 256 rows, a refresh must occur every 15.6us (4ms/256).
– For the 8086, a read or write occurs every 800ns .
– This allows 19 memory reads/writes per refresh or 5% of the time.
• DRAM technologies
–
–
–
–
EDO DRAM
SDRAM
DRDRAM
DDR DRAM
• Soft errors occur on DRAMs which often require ERROR DETECTION and/or ERROR
CORRECTION
• A DRAM CONTROLLER is required for using DRAM
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EXTENDED DATA OUTPUT (EDO) DRAM
• Any memory access in an EDO memory (including a refresh) stores the 256 bits in a set
of latches.
• Any subsequent access to bytes in this set are immediately available (without the decode
time and therefore wait states).
• This works well because of the principle of spatial locality, and improves system
performance by 15 to 25 % !
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SYNCHRONOUS DYNAMIC RAM
• In a synchronous DRAM, the control signals are synchronized with the system bus clock
and therefore with the microprocessor
• It allows pipelined read/write operations
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Double Data Rate (DDR) DRAM
• An SDRAM type of memory where data are transferred on both the rising and the falling
clock edge, effectively doubling the transfer rate without increasing the clock frequency
• DDR-200 means a transfer rate of 200 million transfers per second, at a clock rate of 100
MHz
• DDR1 upto 400 MHz
• DDR2 standard allows higher clock frequencies
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Direct Rambus DRAM (DRDRAM)
• A type of dual-edge SDRAM, like DDR, challenging DDR2 as the standard
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ERRORS AND ERROR DETECTION AND CORRECTION
• Electrical or magnetic interference inside a computer system as well as cosmic radiation
can cause a single bit of DRAM to spontaneously flip to the opposite state. (“soft“
errors)
• As the components on DRAM chips get smaller while operating voltages continue to
fall, DRAM chips may be:
– affected by such radiation more frequently since lower energy particles will be able
to change a memory cell's state.
– or since smaller cells make smaller targets individual cells may be less susceptible to
such effects
• A reasonable rule of thumb is to expect one bit error, per month, per
gigabyte of memory
• Systems often use error detection and correction methods to identify and
possibly correct soft errors
–
–
–
–
repetition schemes
parity schemes (74AS280)
cyclic redundancy checks
Hamming distance based checks (74LS636)
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ERROR DETECTION: PARITY
• A parity bit is a bit added to a fixed number of data bits to ensure that the total number of
‘1’s is either odd (odd parity) or even (even parity)
• Therefore, if the number of data bit ‘1’s is odd in an even parity scheme, the parity bit is
‘1’, otherwise it is ‘0’
• Likewise, if the number of data bit ‘1’s is even in an odd parity scheme, the parity bit is
‘1’, otherwise it is ‘0’
• The parity bit is transmitted with the data, and checked by the receiver
• Advantages:
– Only one bit overhead
– Simple digital circuit implementation
• Disadvantages:
– Cannot correct errors, only detect them
– Only detects an odd number of errors
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PARITY EXAMPLE
• Calculate the parity bit for both even and odd parity, for the following sequence
–
–
–
–
–
1001
0001
1000
1000011
Assuming that the last bit is the parity bit (odd parity), determine which data transmission was
successful and which unsuccessful
– 10001010
– 00111011
– 11011101
• Design the circuit that gives the parity bit
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ERROR CORRECTION: REPETITION AND MAJORITY VOTING
• Data are saved (copied) in three different memory elements
• During a memory read, all three memories are accessed and majority voting circuitry decides the
final output.
• Advantages: the possibility of soft errors is practically eliminated
• Disadvantages: Triple(!) memory space is required, and there is a performance and area overhead
caused by the majority voting circuitry
DATA FROM
MEMORY
Majority
voter
Memory
1
Memory
2
Memory
3
DATA TO MEMORY
uP
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EXAMPLE
• Design the majority voting circuit for one memory bit
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DRAM CONTROLLER
• A circuit performing address multiplexing and DRAM control signal generation
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Semiconductor Memory Expansion
• The size of memory devices is usually less than the memory requirements of a computer system.
• In all computers, more than one memory devices are combined together to form the main
memory of the system.
• Any computer must have at least one ROM chip and one RAM chip.
• Word size memory expansion:
– Most memory devices have a word size (number of data lines) of 8 or 16 bits.
– The word size of today’s microprocessors is 32 bits (80386, 80486) or 64 bits
(Pentium)
• Address size memory expansion:
– The size of common memory chips is usually less or in the order of 256M-byte.
– Most personal computers have more than 2 Gbytes of RAM.
– Workstations and other high throughput computers have more than 4Gbytes of RAM.
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Memory Expansion on Motherboards
Memory Expansion
Using 4 SIMMs on
the Motherboard
Memory Expansion
using 4 Memory
Chips on a SIMM
Motherboard
Slot 3
Slot 4
Slot 1
Slot 2
SIMM
SIMM
SIMM
Processor
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Memory Address Size Expansion
• More than one memory devices can be used to expand the number of memory
locations on the system.
• To expand the word size do the following:
– Determine the number of memory chips required, by dividing the required
memory size with the size of the memory devices to be used.
– Connect the data lines of each memory chip in parallel on the data lines of
the processor.
– Connect the address lines of each memory chip in parallel with the low
address lines of the processor.
– Connect the CS lines of each memory device with the high address lines of
the processor through an address decoding circuit..
– Connect together all WR and all RD lines of each memory device.
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Address Size Expansion: (32X4 RAM module using 8X4 RAM chips)
D0
D1
D2
D3
RAM1 D3
D0
RAM2 D3
D0
RAM3 D3
D0
RAM4 D3
0
0
0
0
1
1
1
1
2
2
2
2
A0 3
A1 4
A0 3
A1 4
A0 3
A1 4
A0 3
A1 4
A2 5
A2 5
A2 5
A2 5
6
6
6
6
7
7
7
7
RD WR CS
RD WR CS
RD WR CS
D0
RD WR CS
RD
WR
A0
A1
A2
A3
A4
A5
A
B
CS
A6
Address
Selection
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Y0
Y1
Y2
Y3
2X4 DEC.
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Memory Maps
• Tables that show the addresses occupied by each memory device in a system.
• In the previous example it is assumed
that the processor has only 7 address
line, thus it can address 128 memory
locations.
• The size of the RAM memory
module is 32 bytes, thus the module
can be mapped to occupy one out of
the four available memory blocks in
the memory map.
• The memory block occupied by the
memory module depends on the
connection of the address selection
circuit (AND gate) that enables the
decoder.
A5
A6
A5
A6
A5
A6
A5
A6
00 - 07 RAM 1
08 - 0F RAM 2
10 - 17 RAM 3
00 - 1F
Not
Used
00 - 1F
Not
Used
20 - 3F
Not
Used
00 - 1F
Not
Used
20 - 3F
Not
Used
40 - 5F
Not
Used
18 - 1F RAM 4
20 - 27 RAM 1
20 - 3F
Not
Used
28 - 2F RAM 2
30 - 37 RAM 3
38 - 3F RAM 4
40 - 47 RAM 1
40 - 5F
Not
Used
40 - 5F
Not
Used
48 - 4F RAM 2
50 - 57 RAM 3
58 - 5F RAM 4
60 - 67 RAM 1
60 - 7F
Not
Used
60 - 7F
Not
Used
60 - 7F
Not
Used
68 - 6F RAM 2
70 - 77 RAM 3
78 - 7F RAM 4
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Effect of the Address Selection Circuit
• The memory block occupied by the memory module depends on the connection of the
address selection circuit (AND gate) that enables the decoder.
• Two address lines are used to control the address selection circuit, thus the circuit can be
configured to occupy four different areas in the address space.
Address Selection
Circuit
A5
A6
A6 A5 A4 A3 A2 A1 A0
0 0 0 0 0 0 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0
0 0 0 1 1 1 1
0 0 1 0 0 0 0
0 0 1 0 1 1 1
0 0 1 1 0 0 0
0 0 1 1 1 1 1
0 1 0 0 0 0 0
1 1 1 1 1 1 1
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Address Selection
Circuit
A5
A6
Address Selection
Circuit
A5
A6
Address Selection
Circuit
A5
A6
Mem. Map A6 A5 A4 A3 A2 A1 A0 Mem. Map A6 A5 A4 A3 A2 A1 A0 Mem. Map A6 A5 A4 A3 A2 A1 A0 Mem. Map
00
0 0 0 0 0 0 0 00 Not
0 0 0 0 0 0 0 00 Not
0 0 0 0 0 0 0 00 Not
RAM1
Used
Used
07
0 1 1 1 1 1 1 3F
1 0 1 1 1 1 1 5F Used
0 0 1 1 1 1 1 1F
08
1 0 0 0 0 0 0 40
1 1 0 0 0 0 0 60
0 1 0 0 0 0 0 20
RAM2
RAM1
RAM1
RAM1
0F
1 0 0 0 1 1 1 47
1 1 0 0 1 1 1 67
0 1 0 0 1 1 1 27
10
1 0 0 1 0 0 0 48
1 1 0 1 0 0 0 68
0 1 0 1 0 0 0 28
RAM3
RAM2
RAM2
RAM2
17
1 0 0 1 1 1 1 4F
1 1 0 1 1 1 1 6F
0 1 0 1 1 1 1 2F
18
1 0 1 0 0 0 0 50
1 1 1 0 0 0 0 70
0 1 1 0 0 0 0 30
RAM4
RAM3
RAM3
RAM3
1F
1 0 1 0 1 1 1 57
1 1 1 0 1 1 1 77
0 1 1 0 1 1 1 37
20 Not
1 0 1 1 0 0 0 58
1 1 1 1 0 0 0 78
0 1 1 1 0 0 0 38
RAM4
RAM4
RAM4
7F Used 0 1 1 1 1 1 1 3F
1 0 1 1 1 1 1 5F
1 1 1 1 1 1 1 7F
1 1 0 0 0 0 0 60 Not
1 0 0 0 0 0 0 40 Not
1 1 1 1 1 1 1 7F Used
1 1 1 1 1 1 1 7F Used
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Example: (32X4 RAM module using 8X4 RAM chips - Assume an 8-address line processor)
D3
D3
D0
D3
D0
D3
D0
D3
D0
8x4 RAM 1
A0
8x4 RAM 2
A0
8x4 RAM 3
A0
8x4 RAM 4
A0
A2
A2
A2
A2
RD WR CS
RD WR CS
RD WR CS
RD WR CS
D0
RD
WR
A0
A2
A3
A4
2X4 DEC.
A
B
A5
A6
Y0
Y1
Y2
CS
Y3
A7
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Memory Map for previous example.
• There are three address lines connected on the address selection circuit. Thus there can
be eight different memory map configurations.
• Three possible memory map configurations are shown below.
Address Selection
Circuit
A5
A6
A7
Address Selection
Circuit
A5
A6
A7
Address Selection
Circuit
A5
A6
A7
A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
A7 A6 A5 A4 A3 A2 A1 A0 Mem. Map
0 0 0 0 0 0 0 0 00
0 0 0 0 0 0 0 0 00
Not
Used
1 0 0 1 1 1 1 1 9F
0 0 0 0 0 0 0 0 00
1 0 1 0 0 0 0 0 A0
1 1 1 0 0 0 0 0 E0
0 0 0 0 0 1 1 1 07
0 0 0 0 1 0 0 0 08
0 0 0 0 1 1 1 1 0F
0 0 0 1 0 0 0 0 10
0 0 0 1 0 1 1 1 17
0 0 0 1 1 0 0 0 18
0 0 0 1 1 1 1 1 1F
0 0 1 0 0 0 0 0 20
RAM1
RAM2
RAM3
RAM4
Not
Used
1 1 1 1 1 1 1 1 FF
1 0 1 0 0 1 1 1 A7
1 0 1 0 1 0 0 0 A8
1 0 1 0 1 1 1 1 AF
1 0 1 1 0 0 0 0 B0
1 0 1 1 0 1 1 1 B7
1 0 1 1 1 0 0 0 B8
1 0 1 1 1 1 1 1 BF
RAM1
RAM2
RAM3
RAM4
Not
Used
1 1 0 1 1 1 1 1 DF
1 1 1 0 0 1 1 1 E7
1 1 1 0 1 0 0 0 E8
1 1 1 0 1 1 1 1 EF
1 1 1 1 0 0 0 0 F0
1 1 1 1 0 1 1 1 F7
1 1 1 1 1 0 0 0 F8
1 1 1 1 1 1 1 1 FF
RAM1
RAM2
RAM3
RAM4
1 1 0 0 0 0 0 0 C0
Not
Used
1 1 1 1 1 1 1 1 FF
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Design Example:
Design an 8KX8 RAM module using 2KX8 RAM chips. The module should be connected on
an 8-bit processor with a 16-bit address bus, and occupy the address range starting from the
address A000. Show the circuit and the memory map.
• Number of memory devices needed = 8K/2K
=4
• Decoder needed = 2X4
• Number of address lines on each 2KX8
memory chip = 11
2m = 2K = 21 x 210 = 211  (A0..A10)
• Decoder needed = 2X4
 2 address lines are needed for the decoder.
 (A11..A12)
• Number of address lines needed for the
address selection circuit
= 16 - 11 - 2 = 3  (A13, A14 A15)
ACOE255
Starting Address = A000 = 1010-0000-0000-0000
==> A15 = 1, A14 = 0 and A13 = 1
A13
A14
Address Selection Circuit
A15
A15
0
1
1
1
1
1
1
1
1
1
1
1
A14
0
0
0
0
0
0
0
0
0
0
1
1
Microprocessors I - Frederick University
A13
0
0
1
1
1
1
1
1
1
1
0
1
A12
0
1
0
0
0
0
1
1
1
1
0
1
A11
0
1
0
0
1
1
0
0
1
1
0
1
A10
0
1
0
1
0
1
0
1
0
1
0
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
Mem. Map
0000
Not
Used
9FFF
A000
A7FF
A800
AFFF
B000
B7FF
B800
BFFF
C000
FFFF
RAM1
RAM2
RAM3
RAM4
Not
Used
36
Circuit Diagram
D7
D0
D7
2Kx8 RAM
D0
D0
D7
2Kx8 RAM
D0
D7
2Kx8 RAM
D0
D7
2Kx8 RAM
A0
A0
A0
A0
A10
A10
A10
A10
RD WR CS
RD WR CS
RD WR CS
RD WR CS
RD
WR
A0
A13
A14
A15
ACOE255
A15
2X4 DEC.
A11
A Y0
A12
B Y1
Y2
CS Y3
Microprocessors I - Frederick University
37
Address Decoding
• The physical address space, or memory map, of a microprocessor refers to the range
of addresses of memory location that can accessed by the microprocessor. The size of
the address space depends on the number of address lines of the microprocessor.
• At least two memory devices are required in a microprocessor system: one for the
ROM and one for the RAM.
• In an 8088/8086 the high addresses in the memory map should always be occupied by
a ROM, while the low addresses in the memory map should always be occupied by a
RAM.
• Address decoding is required in order to enable the connection of more than one
memory devices on the microprocessor. Each device will occupy a unique area in the
memory map.
• A memory system is not fully decoded if some of the address lines are not used by the
address decoding circuit or memory. In this case a memory device will occupy more
than one sections in the memory map. This is referred as memory mirroring or
memory imaging.
ACOE255
Microprocessors I - Frederick University
38
Address Decoding Circuits
• A number of types of address decoding circuits can be used in a microprocessor
system.The main issues related to the selection of an address decoding circuit are:
– The time delays introduced by the address decoding circuit. This delays are added to the
access time of the memory devices, and might yield to the insertion of wait states.
– The number of chips required by the address decoding circuit, as well as the complexity of the
circuit (number of tracks required on the board.
• An address decoding circuit must ensure that an address section is occupied by only one
memory device. If two or more devices occupy the same addresses then bus contention
will occur. Bus contention occurs if two of more devices drive the bus at the same time.
Bus contention can be either static or dynamic.
– Static bus contention occurs when two or more devices drive a bus for a prolonged
time period. This might damage some of the components of the system. Static bus
contention might be caused by improper address decoding design, or by other faults
in the system such as a short circuit of the CS of a device to the ground.
– Dynamic bus contention occurs when two or more devices drive a bus for a short
period of time. This might change the logic levels on the bus and cause system
malfunctions.Dynamic bus contention might be caused by improper address
decoding design, or by wrong memory timing analysis.
ACOE255
Microprocessors I - Frederick University
39
Address decoding circuits using Only NAND gates
• A single NAND gate is used to decode each memory device. The inputs of the NAND gate can be
connected on the address lines either directly, or through inverters, according to the required
memory map.
• This decoding circuit has the advantage that it adds a short time delay in the memory path. (td = 2
X gate delay <10ns)
• The disadvantage of this circuit is that too many gates (NAND and NOT) are needed for memory
systems that have a few memory chips. This increases the cost of the system, adds to the
complexity of the PCB board (too many chips and lines) and might create fan-out problems.
A0
A14
A15
A16
A17
A18
A19
ACOE255
MEM 1 A 0
A14
CS
MEM 2
CS
A19 A18 A17 A16 A15 A14
A0
Memory Map
0
0
1
0
1
0
0
28000H
0
0
1
0
1
1
1
2FFFFH
0
1
0
0
0
0
0
40000H
0
1
0
0
0
1
1
47FFFH
Microprocessors I - Frederick University
MEM1
MEM2
40
Address decoding circuits using line decoders and a NAND gate
• One or more line decoders such as the 74LS139 (2 x 4 decoder) or the 74LS138 (3 x 8
decoder) are used to decode(enable) one out of a number of memory device. The CS
inputs of the decoders are enabled by a NAND decoding circuit, according to the
required memory map.
• This decoding circuit has the disadvantage that it adds at least three gate delays in the
memory path.
• The advantage of this circuit is that less gates (NAND, NOT and decoders) are needed
for memory systems that have a number memory chips.
A0
A14
Mem 1 Mem 2
CS
3X8 Dec.
A15
A16
A17
A18
A19
ACOE255
A
B
C
CS
Y0
Y1
Y7
CS
Mem 8
CS
A19 A18 A17 A16 A15 A14
A0
Memory Map
0
1
0
0
0
0
0
40000H
0
1
0
0
0
1
1
47FFFH
0
1
0
0
1
0
0
48000H
0
1
0
0
1
1
1
4FFFFH
0
1
1
1
1
0
0
78000H
0
1
1
1
1
1
1
7FFFFH
Microprocessors I - Frederick University
MEM1
MEM2
MEM8
41
Address decoding circuits using PLDs
• Programmable Logic Devices (PLD) such as the Programmable Logic Array (PLA),
Programmable Array Logic (PAL) or Gated Array Logic (GAL) have replaced the PROM or
EPROM address decoders. These devices are easily programmed using programs such as the
PALASM and EPROM/PLD programmers.
• This decoding circuit has the advantages of the PROM address decoding circuits, with very low
delay added in the memory path. Furthermore these devices have the option of using a copy-bit,
during programming, that disables reading the content of the device, thus copy protect the design.
PAL Programming
PAL
16L8
A15
A16
A17
A18
A19
1
2
3
4
5
6
I1 Q1
I2 Q2
I3
I4
I5
I6 Q8
I10
Mem 1
19
18
CS
CS
Mem 8
12
20
10
CS
Vcc
Gnd
A19 A18 A17 A16 A15 A14
A 0 Memory Map
CHIP DECODER1 PAL16L8
;Pin Assignment
;1
2
3
4
5 6 . . . 10
A15 A16 A17 A18 A19 NC. . . Gnd
0
1
0
0
0
0
0 40000
0
1
0
0
0
1
1 47FFF
0
1
0
0
1
0
0 48000
;11 12 13 14 15 . . . . 18 19 20
NC Q8 Q7 Q6 Q5 . . . Q2 Q1 Vcc
0
1
0
0
1
1
1 4FFFF
EQUATIONS
/Q1 = /A15 * /A16 * /A17 * A18 * /A19
0
1
1
1
1
0
0
1
1
1
1
1
0 78000
Mem8
1 7FFFF
/Q2 = A15 * /A16 * /A17 * A18 * /A19
Mem1
Mem2
/Q8 = A15 * A16 * A17 * A18 * /A19
ACOE255
Microprocessors I - Frederick University
42
Address decoding circuits using comparators
• Comparators, such as the 74LS85 (4-bit) or the 74LS688 (8-bit) can be used as address decoders.
One set of the input lines are connected on the address bus and the other is usually connected
directly to logic 0 or logic 1 according to the required memory map.
• This decoding circuit has the advantages of the PLD address decoding circuits, i.e. only one chip
in needed and the very low delay added in the memory path. Furthermore the second set of input
lines can be connected to dip switches or an O/P port so that the memory map can be easily
modified.
• The disadvantage of this address decoding circuit is that it can enable only one device, unless if it
is combined with other decoding circuits, such as line decoders.
A0
A15
MEM 1
CS
X=Y
X1 X2 X3 X4
+5V
Gnd
A16
A17
A18
A19
ACOE255
Y1 Y2 Y3 Y4
A0
A15
MEM 2
CS
X=Y
X1 X2 X3 X4
Y1 Y2 Y3 Y4
A19 A18 A17 A16 A15
A0
Memory Map
1
0
0
1
0
0
90000
1
0
0
1
1
1
9FFFF
1
1
0
0
0
0
C0000
1
1
0
0
1
1
CFFFF
Microprocessors I - Frederick University
MEM1
MEM2
43
Address decoding example
Show how a 128Kbyte RAM module can be connected on an 8088 system using 62256
SRAM chips, occupying the address range starting from the address C0000H. Use the
following address decoding circuits:
1
2
3
4.
Nand decoding circuits
Line decoders
PLD decoding circuit
Comparator decoding circuit
Solution:
62256 SRAM chips:
 256/8 =32  32KX8
Number of chips needed:
 128K/32K = 4
Number of address lines:
 32K = 25K = 25 * 210 = 215
 15 address lines (A0 .. A14)
ACOE255
A19 A18 A17 A16 A15 A14 A13
A0
Memory Map
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
1
RAM1
C7FFF
1
1
0
0
1
0
0
0
C8000
1
1
0
0
1
1
1
1
RAM2
CFFFF
1
1
0
1
0
0
0
0
D0000
1
1
0
1
0
1
1
1
RAM3
D7FFF
1
1
0
1
1
0
0
0
D8000
1
1
0
1
1
1
1
1
Microprocessors I - Frederick University
C0000
RAM4
DFFFF
44
Answer: Using NAND gates
62256
A0
D0
D0
A14
D7
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
8088 System
D7
RD
WR
A0
A19
IO/M'
ACOE255
A15
A16
A17
A18
A19
Microprocessors I - Frederick University
45
Answer: Using a line decoder and a NAND gate
62256
A0
D0
D0
D7
A14
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
8088 System
D7
RD
WR
A0
A19
IO/M'
ACOE255
A17
A18
A19
A15 LS139
A Y0
A16
Y
B
1
E
Y2
Y3
Microprocessors I - Frederick University
46
Answer: Using a PLD decoding circuit
62256
A0
D0
D0
D7
A14
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
8088 System
D7
RD
WR
A0
A19
IO/M'
A15
A16
A17
A18
A19
IO/M'
1
I1
I2
I3
I4
I5
I6
2
3
4
5
6
I10
10
18
17
16
PAL Programming: PAL16L8
Q8
Gnd Vcc
PAL 16L8
ACOE255
19
Q1
Q2
Q3
Q4
12
20
;Pins 1
2
3
4
5 6 . . . 10 11 . . .16 17 18 19 20
A15 A16 A17 A18 A19 MEM. Gnd NC . . . Q4 Q3 Q2 Q1 Vcc
EQUATIONS
/Q1 = /A15 * /A16 * /A17 * A18 * A19 * /MEM
/Q2 = A15 * /A16 * /A17 * A18 * A19 * /MEM
/Q3 = /A15 * A16 * /A17 * A18 * A19 * /MEM
/Q4 = A15 * A16 * /A17 * A18 * A19 * /MEM
Microprocessors I - Frederick University
47
Answer: Using comparators
62256
A0
D0
D0
62256
A0
D0
D7
A14
D7
A14
RD WR CS
62256
A0
D0
D7
A14
RD WR CS
62256
A0
D0
D7
A14
RD WR CS
RD WR CS
8088 System
D7
RD
WR
A0
X=Y
X
X=Y
Y
X
X=Y
Y
X
X=Y
Y
X
Y
Gnd
+5V
A19
IO/M'
ACOE255
A15
A16
A17
A18
A19
Microprocessors I - Frederick University
48
Homework:
Show how a 32Kbyte ROM module can be connected on an 8088 system using 2764
EPROM chips, occupying the address range starting from the address E0000H. Use
the following address decoding circuits:
1
2
3.
4.
5
Nand decoding circuits
A line decoder and a Nand gate
PLD decoding circuit
Comparators only
Line decoder and a comparator
Solution:
Size of 2764 EPROM chips:
A19 A18 A17 A16 A15 A14 A13 A12 A11
A0
Memory Map
Number of chips needed:
Number of address lines:
ACOE255
Microprocessors I - Frederick University
49
Answer: Using Nand Gates only
2764
A0
D0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
8088 System
D7
RD
WR
A0
A19
IO/M'
ACOE255
Microprocessors I - Frederick University
50
Answer: Using a line decoder and a Nand gate
2764
A0
D0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
8088 System
D7
RD
WR
A0
A19
IO/M'
ACOE255
Microprocessors I - Frederick University
51
Answer: Using a PLD decoding circuit
2764
A0
D0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
8088 System
D7
RD
WR
A0
A19
IO/M'
ACOE255
Microprocessors I - Frederick University
52
Answer: Using comparators only
2764
A0
D0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
8088 System
D7
RD
WR
A0
A19
IO/M'
ACOE255
Microprocessors I - Frederick University
53
Answer: Using a line decoder and a comparator
2764
A0
D0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
2764
A0
D0
A 12
OE
D7
CS
8088 System
D7
RD
WR
A0
A19
IO/M'
ACOE255
Microprocessors I - Frederick University
54
16-bit Memory Interfacing (8086, 80286, 80186, 80386SX)
• The 8086 differs from the 8088 in three ways:
– The data bus is 16 bits wide instead of 8 bits as on the 8088
– The IO/M’ signal on the8088 is replaced by the M/IO’ on the 8086
– There is a BHE’ (Bus High Enable) signal to enable the upper data bus lines (D8..D15). The
address line A0 behaves as the BLE’ (Bus Low Enable) signal.
• The memory is separated into the High Bank (odd addresses) and the Low Bank (even addresses).
• The 8086 microprocessor can access either the low bank (D0..D7), or only the high bank (D8..D15),
or both banks (D0..D15).
• The is a need only for separate Bank Write Strobes. When the processor reads from the memory,
it always reads both banks, and selects the necessary bank internally.
(BHE')
FFFFF
FFFFD
FFFFB
00005
00003
00001
High Bank (D15..D8)
(Odd Addresses)
ACOE255
(BLE'/A0)
FFFFE
FFFFC
FFFFA
BHE' BLE'(A0)
0
0
1
1
00004
00002
00000
0
1
0
1
Function
Example
Both banks enabled (16 bit) MOV [1000H],AX
High bank enabled (8 bit)
MOV [1001H],AL
Low bank enabled (8 bit)
MOV [1000H],AL
No banks enabled
---------------
Low Bank (D7..D0)
(Even Addresses)
Microprocessors I - Frederick University
55
16-bit Memory Interfacing using separate bank decoders
• The first decoder (left side) is enabled when A0 is zero, thus it is enable with even addresses.
Thus the data lines of the memory devices decoded by this decoder must be connected on the
processor’s data lines D0..D7.
• The second decoder (right side) is enabled when BHE is zero, thus it is enable with odd addresses.
Thus the data lines of the memory devices decoded by this decoder must be connected on the
processor’s data lines D8..D15.
D15
D8
D7
A1
62256
A0
A15 A14
A1
D0
D7
A15
8086 System
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
A1
62256
A0
A15 A14
A1
D0
D7
A15
RD WR CS
A0
D0
A14
D7
RD WR CS
D0
RD
WR
A0
Y0
Y1
Y2
Y3
Y0
1E
A
LS139
A19
BHE'
62256
A
B
Y1
Y2
Y3
LS139
B
1E
IO'/M
A16 A17
A16 A17
A18 A19 A0
ACOE255
Microprocessors I - Frederick University
A18 A19
56
16-bit Memory Interfacing using separate bank write signals
• With this method the decoder always enables both banks.
• On a memory read operation, the data from both banks is loaded on the data bus. The
microprocessor selects internally the appropriate bank, according to the instruction being
executed.
• On a memory write operation, only the WR signal of the appropriate bank is enabled, thus data is
copied only in the appropriate memory chip.
D15
A1
D8
D7
8086 System
A15
62256
A0
D0
A14
D7
A1
A15
RD WR CS
62256
A0
D0
A14
D7
RD WR CS
A1
A15
62256
A0
D0
A14
D7
RD WR CS
A1
A15
62256
A0
D0
A14
D7
RD WR CS
D0
RD
BHE'
WR
A0
A1
Y0
Y1
Y2
Y3
LS139
A
1E
B
A19
IO'/M
A16 A17
A18
ACOE255
A19
Microprocessors I - Frederick University
57
32-bit Memory Interfacing using separate bank write signals
• The 80386 microprocessor has four bank enable signals to select one out of 4 memory banks. The
address lines A0 and A1 are not available.
• On a memory read operation, the data from all banks is loaded on the data bus. The
microprocessor selects internally the appropriate bank, according to the instruction being
executed.
• On a memory write operation, only the WR signal of the appropriate bank is enabled, thus data is
copied only in the appropriate memory chip.
D0
A2
80386 Processor
A16
D31
62256
D0
A0
D0
A14
D7 D7
RD WR CS
A2
A16
62256
D8
A2
A0
D0
A14
D7 D15
A16
RD WR CS
62256
D16
A0
D0
A14
D7 D23
RD WR CS
A2
A16
62256
D24
A0
D0
A14
D7 D31
RD WR CS
RD
WR
BE0'
BE1'
BE2'
BE3'
A2
Y0
Y1
Y2
Y3
LS139
A
1E
B
A17 A18
A31
IO'/M
ACOE255
A19
Microprocessors I - Frederick University
A31
58
Semiconductor Memory Devices:Timing Analysis
• An important parameter of memory devices is the Memory Access Time(tacc). This is the time
measured from the moment that a stable address appears on the address lines of the device, until
the appearance of valid data at the data lines of the device.Another important parameter is the
Chip Select to Output Delay (tcd). If the time allowed by the microprocessor is less than these
parameters then the microprocessor will read the data bus before the memory places the data on
the data bus, thus the microprocessor will read the wrong data.
• The time needed by the memory device to deactivate the output data buffers is also important. The
parameters related to this delay are the Chip Diselect to Output Float (tdf) and the Address to
Output Hold (toh) time. The output buffers must be placed in high impedance before the
microprocessor starts the next memory cycle.
Address
Symbol
tacc
tdh
CS
tdf
tcd
High Z
Data
Timing diagram of the 2764 EPROM
ACOE255
Parameter
tacc
Address to Output Delay
tcd
Chip Select to Output Delay
tdf
Chip Diselect to Output Float
tdh
Address to Output Hold
Min.
Limit
Typ. Max.
250
Unit
450
ns
120
ns
0
100
ns
0
100
ns
AC characteristics of the 2764 EPROM
Microprocessors I - Frederick University
59
Example
• You are asked to interface 8Kx8 bit ROM chips with the following data to a 8088
microprocessor:
• Chip-select to output delay: 70ns(min)
120ns(typ)
180ns(max)
• Address to output delay: 230ns(min)
340ns(typ)
450ns(max)
• Chip deselect to output float:
80ns(typ)
100ns(max)
• Address to output hold:
80ns(typ)
100ns(max)
• Assume that buffers have a delay of 20 ns, and latches a delay of 35 ns. The delay of the
wires is 20 ns
• A. Calculate the number of wait states (if needed)
• B. Draw the corresponding memory read operation timing diagram
• C. Calculate the number of chips required to create a 32Kbyte ROM
• D. Specify the memory map starting from address F8000H
• E. Draw the decoding circuit using NAND gates only
• F. Draw the decoding circuit using a decoder and NAND gates
ACOE255
Microprocessors I - Frederick University
60