Transcript Document

Digital Logic Design
Lecture # 3
University of Tehran
Outline
Review of Lecture #2
Number Systems
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1’s Complement System
Binary Coded System (BCD)
ASCII Code System
Overflow
Designing an Overflow Detector
Structure of NMOS and PMOS Transistors
Designing Logical Gates Using Transistors
Review of Lecture #2


In the last session, we covered three types of coding
(representation) in our look at different number
systems: Binary System, Sign and Magnitude System
and 2’s Complement System.
Quote: The 2’s Complement System was preferred
due to it’s easier arithmetic:
A – B = A + (-B)
0 0 1 1 0 1 0 0 (+ 52)
+
1 1 0 0 1 1 0 0 (- 52)
+
0 0 0 0 1 1 1 0 (+ 14)
0 1 0 0 0 0 1 0
1 1 1 1 0 0 1 0 (- 14)
1 1 0 1 1 1 1 1 0
Review of Lecture #2
(continued…)
0 0 1 1 0 1 0 0 (+ 52)
+
+
1 1 1 1 0 0 1 0 (- 14)
1 0 0 1 0 0 1 1 0

1 1 0 0 1 1 0 0 (- 52)
0 0 0 0 1 1 1 0 (+ 14)
1 1 0 1 1 0 1 0
Note: The 2’s complement system is unbalanced,
meaning that there is always one more negative
number represented than the positive numbers. In
the 2’s complement system with 4 bits, numbers
range from -8 to +7, and there’s no representation
for +8.
Review of Lecture #2
(continued…)
1 0 0 0
1 0 0 1
-8
-7
1 0 1 0
1 0 1 1
1 1 0 0
-6
-5
1 1 0 1
1 1 1 0
1 1 1 1
-4
-3
-2
-1
0 1 1 1
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0 0 1 0
0 0 0 1
0 0 0 0
7
6
5
4
3
2
1
0
Number Systems
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1’s Complement System
Binary Coded System (BCD)
ASCII Code
1’s Complement System
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This system was more widely used historically.
Unlike the 2’s complement system, this system is
balanced.
1 0 0 1
0 1 1 1
-7
7
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
1 1 1 0
1 1 1 1
0 0 0 0

-6
-5
-4
-3
-2
-1
0
0
0
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0 0 1 0
0 0 0 1
0 0 0 0
6
5
4
3
2
1
+
0
When 1’s complementing a number, we simply
change the value of each bit in the representation.
1’s Complement System
(continued…)
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It’s main setback is that it doesn’t perform as well as
the 2’s complement system in arithmetic operations.
This is because the results need adjusting after
addition and subtraction.
In order to adjust the results of addition and
subtraction, it is necessary to add carry with the
result if the operation has had a carry. Example:
00101011
- 00001101
negating
00101011
+ 11110010
carry
1 00011101
1
+
00011110
Binary Coded System (BCD)
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Number system are not always used for arithmetic.
Thus a number system such as BCD that could
represent digits separately would give a positive state
of thought in some cases.
An example for the case mentioned above can be
viewed in storage of phone numbers where we may
need to have quick looks at some particular digits in
an application. Using the number systems mentioned
so far to achieve this would be rather unsatisfactory.
BCD (continued…)
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Here, instead of binary representation of the whole
number, we represent each digit of the decimal
number in binary code. Using this process, we can
easily distinguish between decimal digits in our finally
binary represented number if needed.
The main problems with this system would be in the
arithmetic arena which we had overlooked in the first
place. We also have easier conversions in the BCD
form but are using up more memory to store our
numbers.
BCD (continued…)
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In this number system we need to be able to
represent numbers from 0 through 9 for which we
use 4 bit numbers from 0000 through 1001.
ASCII Code System
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In some application storing text is the most important
of all. The ASCII code is used for this mean.
The digit 0 through 9, lowercase and uppercase
letters all have specific codes in this system.
Today, an extended ASCII table is also used
alongside the basic one which contains the codes of
foreigner letters.
ASCII Code System
(continued…)
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8 bit codes are used to represent the ASCII codes,
where the leftmost digit specifies which table a
specific code belongs to. Codes starting with 1 are
from the extended ASCII table and those starting
with 0 belongs to the basic one.
Special characters are also included in the ASCII code
range. It’s also true about the control characters.
ASCII Code System
(continued…)
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Control characters (first 2 columns) are not printable
and only perform particular actions when used. For
instance:
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BEL: The printer beeps.
BS: A backspace will be made on the printer.
LF: Cursor is sent to the next line.
FF: Page must be ejected from the printer.
CR: The cursor is sent to the beginning of the line.
ASCII Code System
(continued…)
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The control codes used to be used much more in
older systems, and nowadays they are usually
recognized with a combination of “ctrl” + “the first
uppercase alphabetical letter in the same row”
instead of memorizing the related codes.
Overflow
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We shall show this concept through the following
example:
0 0 1 1 0 1 0 0
+
0 1 1 0 1 0 0 0
1 0 0 1 1 1 0 0
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As can be seen above, a negative result has occurred
from the addition of 2 positive numbers. This can
not be an acceptable answer. The result could have
been shown correctly in 9 bits, but our system has at
most 8.
Overflow (continued…)
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Note: Overflowing can be caused by adding large
negative or positive numbers. It’s clear that adding a
negative number and a positive one can not cause
overflow.
Note: A way for pointing out an overflow occurrence
is when the sign bit of the result differs from that of
the operands (if the operand’s sign bits are the
same).
Overflow (continued…)
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Diminishing overflows can be accomplished by
extending the space or numbers are stored in, for
example to 16 bits. Using this method in the first
case shown in the latter slides can be now seen as:
+
0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0
0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0
0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0
Overflow (continued…)
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Extending the size of storage must be done with
consideration of the number’s sign. This is done by
the use of the “Sign-Extension Process” where the 8
left most bits (16,32,… left most bits-dependent on
the size of our actual number) of our new number
are filled with the actual numbers’ sign bit.
Designing an Overflow
Detector
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The circuit we are about to design will need three
inputs for it’s aim. The first and the second
operands’ sign bit and also the sign bit of the sum.
A
B
Adder
a
b
s
OV
v
Designing an Overflow
Detector (continued…)
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The problem, we face, can be solved with the
following insight to it. In words we have: “Overflow
occurs when:
a=0 and b=0 and s=1
or
a=1 and b=1 and s=0”
Changing the sentence above and closing the gap
between the English statement and the math logic,
we have:
v  a.b.s  a.b.s
Designing an Overflow
Detector (continued…)
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If we state the equation using the following symbols,
we have:
NOT
b
s
AND
OR
a
v
Structure of NMOS and PMOS
Transistors
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The structure of a typical transistor is something like
Gate
SiO
this:
Source
Drain
2
channel
Body
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A transistor conducts when the channel between the
source and drain is filled with carriers. In a NMOS
transistor, the channeling is done by negative carriers
(free electrons) and in PMOS transistors, it is done by
positive carrier (holes electrons in the capacity
band).
Designing Logical Gates Using
Transistors
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Now we will attempt to put together combinations of
these transistors to serve the needed purpose of the
mentioned logical gates.
The gate “NOT” (inverter):
vdd
a
w
a
0
1
w
1
0
Symbol
Designing Logical Gates Using
Transistors (continued…)
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As it can be obviously seen in the previous figure, a 0
input will make the PMOS transistor conduct and the
NMOS one not conduct, resulting in a 1 output and a
1 input will have the output pulled down to 0 through
the NMOS transistor.
Designing Logical Gates Using
Transistors (continued…)
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The gate “NOR”:
vdd
a
b
w

a
0
0
1
b
0
1
0
w
1
0
0
1
1 0
Symbol
If either of the 2 PMOS transistor doesn’t conduct,
the supply will not reach the output whereas the
output will be 0 if either of the NMOS transistors
conducts. This structure of transistors serves the
NOR function.
Designing Logical Gates Using
Transistors (continued…)
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The gate “NAND”:
vdd
w
a
b

a
b w
0
0
1
1
0
1
0
1
Symbol
1
1
1
0
This structure can serve as NAND, the output being 0
only when the 2 inputs are 1 simultaneously.
Designing Logical Gates Using
Transistors (continued…)
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Note: Using three input in each of the serial or
parallel parts of these circuits will give the structure
of a three input NAND/NOR notation.