Transcript Chapter 6

Chapter 6
(1) Long cycle time
(2) Idle transistors
Notice: Cycle time 200, even though some stages shorter
Need registers between stages, just as in multi-cycle version
(discuss each of the five stages)
Need separate instruction
And data memories
Need more than one ALU
Structural hazard: Trying to use same hardware
to do two different things at
once
$s0 still here
When needed here
Data hazard: Data from previous instruction not
“ready” to be used by next instruction
$s0 needed here, but
not written until here
Solutions???
Solution #1:
Stall
Solution #2: Data forwarding: Use data before it’s written
Control Hazard: Making decisions based on uncomputed data
When do we know whether we’ll branch?
So, what instruction do we load next?
One solution: Stall
We’ll discuss better solutions later