Transcript November04 large power point presentation

Device Modelling in the New Silicon Era
& the future with silicon
John Barker
Nanoelectronics Research Centre
Department of Elelectronics and Electrical Engineering
University of Glasgow
UK SiGe Research Programme
EPSRC
Final Review Meeting, Thursday November 4th 2004
Electrical and Electronic Engineering Dept, Imperial College,
Human Resources
John Barker
Asen Asenov
Scott Roy
Jeremy Watling
Savas Kaya
Mirela Borici
Richard Wilkins
Lianfeng Yang
Antonio Martinez
Outline
Deliverables:
Publications, Conferences, Grants, Collaborations
Context: where we are with Si and SiGe (update)
Theory and Modelling:
3D atomistic Full Band Monte Carlo,
3D Non-equilibrium Green function atomistic simulator
3D NASA codes
High  dielectrics
Devices: conventional versus strained Si MOSFETs
Nano-silicon and atomistic MOSFETs
 The future with silicon
(I come to bury silicon not to praise it!)
Deliverables in Phase I-II (2001-2004): I
Publications: > 50 (major journals inc IEEE Trans)
Review paper:”The impact of interface roughness scattering and degeneracy
in relaxed and strained Si n-channel MOSFETs”
Solid State Electronics, 48, 1337-1346 (2004)
Special mention:”I am pleased to tell you that your article,
"Si/SiGe heterostructure parameters for device simulations", in Semiconductor
Science and Technology, Vol 19, pp1174 (2004), has been downloaded 250 times
so far.To put this into context, across all IOP journals 10% of articles were
accessed over 250 times this quarter.”
Conferences: IEDM, ESSDERC, Si-VLSI, ICPS26, ICPS27, VLSI02,03,04
CMMP04,SISPAD,NEGF2,MSED03,EDSSC03,
EDMO,ULSI04,ICSIT04,IWCE9, SIMD-6,NPMD03,
HCIS13, IWCE10,HighKWorshopAustin04,Sematech Symp
Invited papers: 12
Special notice: Paper accepted for IEDM’04.
Deliverables (2001-2004): II
New Grants and Collaborations
1.
2.
3.
4.
5.
6.
Statistical 3D simulation of intrinsic parameter fluctuations in decananometer
MOSFETS introduced by discreteness of charge and matter
A Asenov, J.R. Barker, S Roy, J Watling EPSRC HPC facility EPSRC 01/10/0430/09/04 £ 153021
Modelling the impact of high-k gate stacks on mobility device performance and
intrinsic parameter fluctuations
J. Watling , A. Asenov ,J.R.Barker, S. Roy; and UCL; International Sematech
09/2004-10/2006 $ 310 000
SINANO - Network of Excellence A. Asenov , J.R. Barker,S. Roy IMEC, LETI,
INFINEON, ST MICROELECTRONICS European Commission 01/200402/2007 € 250 000
Sub 100 nm III-V MOSFETs for Digital Applications With 14 others
MOTOROLA, University of Surrey EPSRC 09/2003-09/2006 £ 3000 000
Meeting the materials challenges of nano-CMOS electronics
A Asenov, J.R. Barker and S Roy collaboration with University College London
and NASA Ames EPSRC, 01.07.04-30.06.08: £ 354711
Atomistic simulation of nanoscale devices A Asenov, J.R. Barker, S Roy
EPSRC Platform grant, 06.02-05.07: £ 429564
Other stuff
Intel using SiGe/Si hole
band model for compact
studies.
Sharing atomistic codes
NASA 2D and 3D NEGF
codes to be shared with
Glasgow
Our 3D atomistic NEGF
codes to be shared with
NASA
INDUSTRY: IBM, Intel,Toshiba
NASA, Sony, Freescale…
DFT collaborations
underway
Context: where we are with Si and SiGe
2002
International Technology Roadmap 2001 Edition
Year
2001 2004 2007 2010 2013 2016
130
90
65
45
32
22
Technology node (nm)
65
37
25
18
13
9
MPU Gate Length (nm)
1.3-1.6 0.9-1.4 0.6-1.1 0.5-0.8 0.4-0.6 0.4-0.5
Oxide thickness (nm)
ITRS 1999
ITRS 2001
a
a
a
a
a
a
a
a
a
a
AMD Dec 2001
Intel May 2002
IBM Dec 2002
The dramatic acceleration of the ITRS is due to the failure of
conventional MOSFETs to meet the performance requirements.
Brute force scaling of MOSFETS will not work
Intel
Requires
Too thin oxide
Too high doping
Toshiba
Too Hot
Results in
High leakage
Gate oxide and band to band tunnelling
Low performance
Intel
Impurity scattering limited mobility
Intrinsic parameter variations
Random dopants and interfaces
10 nm
The conventional MOSFET will need a replacement somewhere
between the 65 nm and the 45 nm technology nodes.POST CMOS
The IBM 6 nm silicon transistor (IEDM 2002)
demonstrated
New Post CMOS architecture solves problem
Context: where we are with Si and SiGe 2004
Research pushes MOSFET designs down to 4-5 nm
High K dielectric take-up is high(gate leakage stopped dead)
Some problems in old CMOS yield at 90 nm node IBM. Intel
Parallel track developing: Plan A-aggressive scaling
Plan B-multi-core and other
architecture developments
NoC/SoC
SiGe and strained silicon:
Huge interest: definitely on board for coming generations
The Post CMOS Si developments have two mainstreams
New materials
New device architectures
SiGe, Ge, Strained Si
UTB SOI, Multiple gates
Lower effective mass
Increased mobility
Reduced scattering
Higher carrier velocity
Ballistic transport
Better electrostatic integrity
Reduced SCE
Improved drivability
Relatively thicker oxide
Ballistic transport
Improves device
performance compared to Si
High K: new issues
Allows scaling to nanometer
dimensions
Members of the SiGe consortium have carried out pioneering work in
these two mainstream areas.
The Post CMOS devices are immensely complex from physics
and technology point of view
Double-gate
Fin-FET
SON
SiGe
Omega-gate
UTB SOI
Quantum
Strained Si
Confinement
Pure Ge
Tunnelling
High-K
Non-equilibrium
TiN
10 nm DG MOSFET
NiSi
Metal gate
Ballistic
Schottky S/D
Replacement gate
Raised S/D
Silicon is once again an exciting area for research.
Huge challenge for device modelling
Atomistic
Mobility in UTB SOI
K. Ushida IEDM 02
Quantum potential variation
Associated with UTB variation
Scattering from two interfaces
Surface phonons
TO phonons coupling
Remote Coulomb scattering
Interface charge scattering
Body thickness fluctuations
Material composition fluctuations
High-k composition fluctuations
Complexity associated with the simulation of thin body SOI MOSFETS
Device quantum effects at room temperature
Gate
Tunnelling
B-to-B
Tunnelling
Quantum transport
Quantum
Confinement
S-to-D
Tunnelling
And this is only one item from the list on the previous slide.
Technology nodes 22 nm
SOI
30nm
0.25 m2
6 nm
channel
Toshiba (2004)
5 nm wire FINFET
Taiwan Semiconductor Manufacturing company
High-k
SiGe(:C)
Motorola
LETI/STM
Univ. Texas
Theory and Modelling:
Tools: unique to UK
Helps understand the present
Helps design the future
Used to iteratively design and model devices for Cons.
3D Atomistic Monte Carlo
3D Non-equilibrium Green function atomistic simulator
3D NASA codes
Medici
Quantum corrected Medici
Planned: atomic basis sets, DFT,
Quantum corrected Monte Carlo
Convergence with quantum chemistry
Two recent examples
1. High- dielectrics
• Scaling
•
of MOSFETs beyond the 45nm technology node
required by 2010 (ITRS) requires extremely thin SiO2 gate
oxides (~0.7nm) resulting in intolerably high gate leakage.
 high 
Maximise gate capacitance: C   ox t

t
ox
t ox
high

 SiO2
  ox 
• The
most likely solution is the implementation of high-
dielectrics such as HfO2 and Al2O3 which are the leading
contenders. However, there is afundamental drawback due
to the resulting mobility degradation.
Strained Si
• Has
already demonstrated significant enhancement for
CMOS applications. It is shown here that it can compensate
for the performance hit due to high k dielectric.
2.
Interface roughness
(new non-perturbative model in excellent agreement with expt)
Full SC Quantum
Gaussian auto-covariance
Exponential auto-covariance
Ab initio models
Parameters: RMS height, 0.5nm and Correlation Length, c=3.0nm
M. Boriçi, J. R. Watling, R. Wilkins, L. Yang and J. R. Barker,
J. Comp. Electronics, 2 p163-167 (2004)
Device Structures investigated
Simulation of 67nm IBM Relaxed and Strained Si n-MOSFET
Impact of Surface Roughness Scattering
Comparison between n-type
Strained Si and control Si
MOSFETs:
• 67nm effective channel length
• Similar processing and the
same doping conditions
In the strained Si MOSFET:
• 10nm tensile strained Si layer
• Strained Si on relaxed SiGe
(Ge content: 15%)
K.Rim, et. al., Symposium on VLSI Technology 2001
http://www.research.ibm.com/resources/press/strainedsilicon/
Strained Si n-channel MOSFET Structure
Comparison between the n-type Strained Si
and control Si MOSFETs:
• 67nm effective channel length
• Similar processing and doping conditions
• Oxide thickness, tox =2.2nm (SiO2)
For the strained Si MOSFET:
• 10nm strained Si layer thickness
• Strained Si on relaxed SiGe
(Ge content: 15%)
SiGe n-MOSFET >35% drive current enhancement
(70% high field mobility enhancement)
Universal Mobility Curve: Monte Carlo v Expt
Si
SSi
RMS
0.5nm 0.5nm
CL
1.8nm 3.0nm
A smoother interface
for strained Si?
‘universal’ mobility behaviors of bulk Si and strained Si, a
comparison between experiment and Monte Carlo
simulation.
Device Calibration – Drift Diffusion
Drift-diffusion (MEDICI™) device
simulations
• Concentration dependent, CaughyThomas and perpendicular field
dependent mobility models
• Corrected Si/SiGe heterostructure
parameters: band gap and band
offsets, effective mass, DoS and
permittivity†
Calibrated ID-VG characteristics of the 67nm n-type bulk Si and
strained Si MOSFETs (experimental data from Rim VLSI’01)
L. Yang, et al, ‘Si/SiGe Heterostructure Parameters for Device Simulations’,
Semiconductor Science and Technology (2004)
†
Device Calibration – Monte Carlo
Larger CL
For SSi
Smoother
interface
Performance
Enhancement
Calibrated ID-VG characteristics for 67nm conventional Si and strained
MOSFETs, comparison with experimental data of Rim.
Problems associated with high- dielectrics
(1) Lower mobility (Soft optical phonon scattering)
(2) Micro crystal growth
(3) Lateral oxidation at gate edge
(4) Interfacial layer formation  Fermi level pinning
(5) Fixed charge, Flatband shift
(6) Higher density of interface states
(7) Reliability
Atomic level modelling
Iwai, ESSDERC’03
Strong SO phonon scattering degrades the
inversion layer carrier mobility within the MOSFET
with high- gate stacks.
Adapted from: Hitachi IEDM 2003
Atomic level models needed
Remote (SO) Phonon Scattering
SO phonon scattering rate in the X-valley for phonon mode 1
(absorption) as a function of energy and the distance from interface
(HfO2 EOT=2.2nm for bulk Si MOSFET)
Monte Carlo simulations of Si MOSFET
and SSi MOSFET with HfO2 oxide
The losses due to high k in Si are largely compensated
by switching to high k in strained silicon.
See IEDM paper
Monte Carlo simulations of Si MOSFET,
with Al2O3 oxide
Note
SSi
Restores
Performance
hit
ID-VG characteristics of 67nm n-type Si MOSFET, with and without
soft-optical phonon scattering, from the Al2O3 oxide.
Summary of high K results
• We have investigated the impact on the performance degradation in
sub 100nm n-MOSFETs due to soft-optical phonon scattering in the
presence of high- dielectrics HfO2 and Al2O3.
• A device current degradation of around 25% and 10% at VGVT=1.0V and VD=1.2V is observed for conventional and strained Si
devices with a 2.2nm EOT HfO2 or Al2O3 dielectric respectively.
• Results indicate that the performance degradation associated with
high- gate stack MOSFETs can be compensated by the
introduction of strained Si channels.
• The infancy of high- gate fabrication techniques means that overall
performance degradation associated with high- gate dielectrics is
expected to be worse than the predictions here.
More details in IEDM paper.
Nano-silicon and atomistic MOSFETs
New methodologies for the challenges ahead:
planned or in hand.
Convergence with Quantum Chemistry
Atomic basis functions
Density Functional Theory
Non Equilibrium 3D Green Function codes
Quantum corrected Monte Carlo
Extensions to quantum corrected drift diffusion
Convergence with Quantum Chemistry
Basis for exploring hybrid technologies and
Ultimately nano-molecular electronics.
Huge range of new materials/device configs, with
industry looking for answers soon.
The next generation Post-CMOS devices are immensely
complex from physics and technology point of view
Double-gate
Fin-FET
SON
SiGe
Omega-gate
UTB SOI
Quantum
Strained Si
Confinement
Pure Ge
Tunnelling
High-K
Non-equilibrium
TiN
10 nm DG MOSFET
NiSi
Metal gate
Ballistic
Schottky S/D
Replacement gate
Raised S/D
Silicon is once again an exciting area for research.
Huge challenge for device modelling
Atomistic
Quantum simulations and Green Function Codes
Exotic science discovered in
advanced Si devices
10-25 nm
Fluctuations in
device performance
Current flow comprises open orbits + localised vortices
Discovered at Glasgow, picked up by IBM, ASU
Existence of vortices in total current at high T
Exact model and NEGF
Simulations in 3D
 1
Decoherence studies in 3D

N
m * r2
Barker and Martinez 2004
CONCLUSIONS: The future with silicon
EPSRC has given the UK community
the opportunity to stay in world-class competition
in the technology of the century.
But it will not be enough to continue to compete
in Europe, let alone the world.
Silicon technology of the type available to develop new
applications and systems is BIG ENGINEERING.
We need to shift away from
the gentlemanly amateurism of the 1970s and 1980s
which saw us lose our world lead in semiconductors.
The future with silicon
The UK cannot afford not to be in silicon
It will remain the platform technology for at least 20 years
as scaling continues.
It will remain a platform for maybe
>20 years beyond, by supporting System on Chip,
Network on Chip, Comms on chip, Lab on chip, Smart dust,
Nanorobotics, Med.Diagnostic on Chip, Nanotechnology,
Hybrid organic/plastic silicon/
Some questions and observations
Can you name any replacement technology?
Remember: it is not good enough to demonstrate a transistor
or even two. Can you demonstrate any path to fabricating
1000000000000 transistors, precisely, at low cost in 16 mm2
and repeat this for 16000000000 chips?
The future with silicon
What opposition? Does exotic science gave any solitions?
Single Electronics: no gain, RC time constant limited,very slow
Sensitive to local fluctuations. Compensating circuitry
outweighs SET circuitry at 256 M level.No fabrication strategy.
Nanotubes: Millie Dresselhaus let the cat out of the bag in
ICPS27. Every CNT has its own name: they are all different
and massively sensitive to contaminants.
There is absolutely no interconnection strategy, no fabrication
strategy.
Even magnetic bubble logic was better advanced.
Don’t believe the hype!
The future with silicon
Spintronics: similar issues to single electronics. Also scales.
Wave interference devices: in your dreams!
You need 30000 electrons just to resolve a 2 slit experiment.
Scale, coherence/de-coherence. The interface between macro
Micro system…… Already dismissed in the 1980s.
Molecular electronics: most simple molecules are already the
scale of 5 nm MOSFETs. Huge problems of fabrication and
Interconnection. Absolutely no assembly method demonstrated,
Unless you count DNA replication (error rate 10-5!!).
3D might just be an advantage; likely to be very slow.
Nice non-competitive apps: still need to interface to silicon.
Biological devices: surely not neurons or biomachines!!
The future with silicon
III-V MOSFETs: the window of opportunity is narrowing. At
the smallest scales there is no advantage. But could
integrate with silicon or germanium.
(IBM, IWCE04)
Silicon and SiGe are already encroaching on III-Vs for RF
Quantum Computing: the idea of several bits on one
electron and the mystical advantages of QC fascinates a
lot of people. Ask them what real advantages it has over
analogue computing? Do you really expect to control
coherence/entanglement etc at room temperature?
DNA computers: fascinating demos. Totally ludicrous as
engineering.
If you want more emergent technologies that will replace Si
Remember the characteristic of Pseudo-Science
The future with silicon
How many more times does the UK have to get it wrong in
Electronics? The issue is primarily engineering.
Remember: Babbage
Malvern 3D ICs in 1950s 1960s;
GaAs, III-Vs, InP, Bubble logic, Gunn logic, Resonant tunnel
devices, High Tc and Low Tc superconducting systems,
…….
So, you whine….” It is in the Road Map;
All the new stuff you disparage is IN THE ROAD MAP.”
“..and the non Silicon Physics community says that silicon
is dead!”
The future with silicon
Let me tell you about the reality of the Road Map.
It is supposed to be a wish list of problems to solve in order to
continue Moores Law. It was originally.
Now manufacturers lower the targets, so that they triumphantly
beat the Road Map. Usually each year at IEDM.
Remember the HEAT DEATH of NMOS ? We got CMOS.
Remember the recent HEAT DEATH scares of CMOS?
Lots of solutions: raised S/D, Si on insulator, high k dielectrics, …
What about the new emergent technology section?
Mostly pie in the sky. This is where the gurus play.
It is also cool for investors to know that your favourite company
invests in the future. But test it: you are scientists: how much are
they actually spending? Eg look at Intels CNT investment.
The future with silicon
Of course there are problems, but there is a surfeit of routes forward
Most involve new science tightly integrated with new engineering.
Of course there are limits. But not to applicable electronics.
We will still want low cost super-functionality from future chips.
But they will not just be memories and CPUs.
New materials, new devices will be hybridised and developed
using that special economic advantage of silicon:
the cost per function is likely to fall even as the functionality
increases and diversifies.
The next decades should be periods of great invention.
We will need access to silicon fabrication to explore new
inventions. Off the shelf is simply not good enough.
The industry needs help in the development of the next
generations devices
The technology is so complex that even the large multinationals can
not afford to develop it alone (groupings for developing 65 nm node).
During the downturn the multinationals downsized their basic
research capabilities and cannot deal with some of the material, device
physics and modelling issues.
The companies are therefore ready to forge new relations with
universities and to offer not only financial contribution but access to
technologies and devices.
Strong alliances has been developed in the European scene in
Framework 6 including members of the consortium (SINANO,
NanoCMOS).
University research is bound to play an important role in the
Nano-CMOS era.
The ex members of the SiGe consortium are particularly well placed
due to pioneering research in materials, device physics and design,
semiconductor theory and modelling and Si fabrication
Not the end…
New beginnings!!