Transcript Lezione 3

MICROELETTRONICA
DC and transient responses
Lezione 3
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Outline
Outline
•
•
•
•
DC Response
Logic Levels and Noise Margins
Transient Response
Delay Estimation
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DC Response
• DC Response: Vout vs. Vin for a gate
• Ex: Inverter
– When Vin = 0 ->
Vout = VDD
– When Vin = VDD
->
Vout = 0
– In between, Vout depends on
transistor size and current
– It’ clear that we must settle
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
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Beta Ratio
If βp / βn  1, switching point will
move from VDD/2
Called skewed gate
Other gates: collapse into
equivalent inverter
VDD
p
 10
n
Vout
2
1
0.5
p
 0.1
n
0
Vin
VDD
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Noise Margins
How much noise can a gate input see before it does
not recognize the input?
Output Characteristics
Logical High
Output Range
VDD
Input Characteristics
NMH
VIH
VIL
NML
Logical Low
Output Range
Logical High
Input Range
VOH
VOL
Indeterminate
Region
Logical Low
Input Range
GND
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Logic Levels
To maximize noise margins, select logic
levels at unity gain point of DC transfer
characteristic
Vout
Unity Gain Points
Slope = -1
VDD
VOH
 p/ n > 1
Vin
VOL
Vout
Vin
0
Vtn
VIL VIH
VDD- V
DD
|Vtp|
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Capacitance
• Any two conductors separated by an
insulator have capacitance
• Gate to channel capacitor is very important
– Creates channel charge necessary for operation
• Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion
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Gate Capacitance
• Approximate channel as connected to
source
• Cgs = eoxWL/tox = CoxWL = CpermicronW
• Cpermicron is typically about 2 fF/mm
polysilicon
gate
W
tox
n+
L
n+
SiO2 gate oxide
(good insulator, eox = 3.9e0)
p-type body
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Diffusion Capacitance
• Csb, Cdb
• Undesirable, called parasitic capacitance
• Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
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Transient Response
• DC analysis tells us Vout if Vin is constant
• Transient analysis tells us Vout(t) if Vin(t)
changes
– Requires solving differential equations
• Input is usually considered to be a step or
ramp
– From 0 to VDD or vice versa
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Inverter Step Response
Ex: find step response of inverter driving load cap
Vin (t )  u (t  t0 )VDD
Vout (t  t0 )  VDD
Vin(t)
Vout(t)
Cload
dVout (t )
I dsn (t )

dt
Cload

0


2

I dsn (t )  
V

V


DD
2

V (t )
  VDD  Vt  out 2
 
Idsn(t)
t  t0
Vin(t)
Vout  VDD  Vt
 V (t ) V  V  V
 out
out
DD
t

Vout(t)
t0
t
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Operating Regions
VDD
Region nMOS
A
Cutoff
B
Saturation
C
Saturation
D
Linear
E
Linear
pMOS
Linear
Linear
Saturation
Saturation
Cutoff
A
B
Vout
C
D
0
Vtn
VDD/2
E
VDD+Vtp
VDD
Vin
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Delay Definitions
• tpdr: rising propagation delay (maximum time)
– From input to rising output crossing VDD/2
• tpdf: falling propagation delay (maximum time)
– From input to falling output crossing VDD/2
• tpd: average propagation delay
– tpd = (tpdr + tpdf)/2
• tr: rise time
– From output crossing 0.2 VDD to 0.8 VDD
• tf: fall time
– From output crossing 0.8 VDD to 0.2 VDD
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Delay Definitions
• tcdr: rising contamination delay (minimum
time)
– From input to rising output crossing VDD/2
• tcdf: falling contamination delay (minimum
time)
– From input to falling output crossing VDD/2
• tcd: average contamination delay
– tpd = (tcdr + tcdf)/2
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Simulated Inverter Delay
• Solving differential equations by hand is too hard
• SPICE simulator solves the equations numerically
– Uses more accurate I-V models too!
• But simulations take time to write
2.0
1.5
1.0
(V)
Vin
tpdf = 66ps
tpdr = 83ps
Vout
0.5
0.0
0.0
200p
400p
600p
800p
1n
t(s)
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Delay Estimation
• We would like to be able to easily estimate delay
– Not as accurate as simulation
– But easier to ask “What if?”
• The step response usually looks like a 1st order RC
response with a decaying exponential.
• Use RC delay models to estimate delay
– C = total capacitance on output node
– Use effective resistance R
– So that tpd = RC
• Characterize transistors by finding their effective R
– Depends on average current as gate switches
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RC Delay Models
• Capacitance proportional to width
• Use equivalent circuits for MOS transistors
– Ideal switch + capacitance and ON resistance
– Unit nMOS has resistance R, capacitance C
– Unit pMOS has resistance 2R, capacitance C
• Resistance inversely proportional to width
d
g
d
k
s
s
kC
R/k
kC
2R/k
g
g
kC
kC
s
d
k
s
kC
g
kC
d
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Example: 3-input NAND
• Sketch a 3-input NAND with transistor widths chosen to
achieve effective rise and fall resistances equal to a unit
inverter (R).
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Elmore Delay
• ON transistors look like resistors
• Pullup or pulldown network modeled as RC ladder
• Elmore delay of RC ladder
t pd 
R
i to  source
Ci
nodes i
 R1C1   R1  R2  C2  ...   R1  R2  ...  RN  CN
R1
R2
R3
C1
C2
RN
C3
CN
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Delay Components
• Delay has two parts
– Parasitic delay
• 6 or 7 RC
• Independent of load
– Effort delay
• 4h RC
• Proportional to load capacitance
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Contamination Delay
• Best-case (contamination) delay can be substantially less
than propagation delay.
• Ex: If both inputs fall simultaneously
2
2
A
2
B
x
2
6C
Y
4hC
2C
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Diffusion Capacitance
• We assumed contacted diffusion on every s / d.
• Good layout minimizes diffusion area
• Ex: NAND3 layout shares one diffusion contact
– Reduces output capacitance by 2C
– Merged uncontacted diffusion might help too
2C
Shared
Contacted
Diffusion
2C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
2
2
2
3
3
3C 3C 3C
3
7C
3C
3C
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