Transcript Digital Logic Design

Digital Logic Design
Lecture # 18
University of Tehran
Outline
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Other Kinds of Flip Flops
Dynamic Logic
Sequential Circuit Design
Designing a 110 Detector
Other Kinds of Flip Flops
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Last session we saw a D flip flop with a master slave
structure, now let’s see a SR flip flop with the same
master slave structure as before. The same
differences between the D latches and master slave
D flip flops can be observed between the
corresponding SR latches and SR flip flops, this
difference being the isolation of data in flip flops.
S
Q
R
c
Other Kinds of Flip Flops
(continued…)
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The problem we had with SR latches still exists in SR
flip flops, that is we can’t have activity on both S and
R lines at the same time. When either of these 2
components is working properly the output lines
should have complemented values, that is when line
1 is set to be high, line 2 must be low and vice versa.
Other Kinds of Flip Flops
(continued…)
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The mentioned problem can be solved by adding the
red feedback lines to the circuit, thus disabling the
set line when the circuit is in its set state and
disabling the reset line when the circuit is in a reset
state. Doing this will not effect ordinary functionality
of our circuit as it doesn’t change our ability in
changing states.
J
Q
K
C
Other Kinds of Flip Flops
(continued…)
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This representation, shows an altered form of the SR
flip flop called a “JK Flip Flop” and can be
represented in the following forms:
Q
J
K
Q+
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
1
1
1
1
0
1
Transition table
1
0
1
0
J
0
0
1
1
K
0
1
0
1
Q+
Q
1
0
_
Q
1J
1K
C1
c
Graphical notation
Q
_
Q
Other Kinds of Flip Flops
(continued…)
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Quote: Structures that work on the clock pulse, such
as JK flip flop are called pulse triggered. Structures
that work with the rising or falling edge of the clock
are called edge triggered, which work slightly faster
than the pulse triggered structures but are less
reliable.
Note: When we look at a pulse triggered and falling
edge triggered on an oscilloscope alongside one
another, they don’t differ much on timing manners
but their structures are completely different.
Other Kinds of Flip Flops
(continued…)
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In the shown JK flip flop, if we connect the J and K
inputs to each other, we have a toggle flip flop that
keeps its output when clocked on a low input and
toggles the output when clocked on a high input.
T Q+
0 Q
1 Q
T
Q
1J
1K
c
C1
Other Kinds of Flip Flops
(continued…)
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Flip flops can always be made from each other using
some discrete logic, for instance consider the
following example. Making a JK flip flop from a D flip
Q
flop:
0
1
JK
00
01
0
1
0
4
0
0
1
11
5
1
3
10
7
1
0
1
2
6
d
J
K
d
Q K  QJ
Q
1D
C1
Dynamic Logic
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The basis of this sequential logic is of the following
shape, instead of the cross coupled gates we have
seen so far:
vdd
C
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This structure which is called a half register stores
the data inputted from the NMOS input as capacity
charge in the inverter when the clock rises to 1, and
will keep the data until the capacitor’s charge starts
to fade.
Dynamic Logic (continued…)
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Using the half register shown, we have the Dynamic
D type master slave flip flop as shown in the figure:
C
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vdd
_
C
vdd
When ‘c’ is 1, data is stored in the first inverter
structure and when it goes 0, data is stored in the
second.
Dynamic Logic (continued…)
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The main problem in these structures in that its data
can quickly fade, and will need refreshing to keep its
amount (that is when it is not clocked with new data
for a while). This refreshing is done by feedbacking
the output to the input as seen in red.
E
C
E
D
vdd
_
C
vdd
Dynamic Logic (continued…)
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Quote: The transistors controlled by signal ‘E’ is
driven by the pull up on the levels that come before
this structure.
Another point that must be taken to mind is that we
use non-overlapping signals c1 and c2, instead of c
and c’ for control signals to avoid any transparency
that may occur otherwise. This structure is called a 2
phase non-overlapping clock structure.
C1
C2
Sequential Circuit Design
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We have seen basic discrete components in
sequential design that are gates and flip flops. In
sequential circuits, there are certain models that are
usually followed. The model we will be using in
which everything happening is synchronized to a
clock that is implicitly part of our circuit is called the
Huffman Model as seen in the following figure:
PI
Comb.
Q
1D
C1
Q
1D
C1
clock
PO
Sequential Circuit Design
(continued…)
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Each sequential circuit that you will see has a
combinational part and a register part where the
register part feedbacks its output to the
combinational part. What we need to be able to
design such circuits with practical speed is a straight
forward method.
We saw that a flip flop (the main part in the register
section of our model) has different representation,
them being: transition table, characteristic equation,
excitation table, state diagram. Among these
different representations, the state diagram is the
nearest to our way of thought.
Sequential Circuit Design
(continued…)
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Using the state diagram as a basis to build on, from
now on, the design flow will run from the problem
description to state diagrams, a transition table and
finally the circuit itself.
Designing a 110 Detector
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As our first design we will see a 110 detector that will
give a high output whenever clocked with such a
sequence on its input.
x
110
w
c
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Obviously such a circuit is sequential because its
output relies on a series of certain inputs in its
history.
Designing a 110 Detector
(continued…)
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Note: In synchronous sequential circuits such as that
of this problem, anything happening when the clock
is in its active state.
Note: When doing our design of sequential circuits
we consider the clock pulse to be implicit and no
gating must be done on this signal.
To do our circuit design of this problem we start from
its state diagram. We may even not know how many
states we need but we work our way through the
different states.
Designing a 110 Detector
(continued…)
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This problem can be the same as looking for a special
sequence of shops when walking along a road.
Consider you are looking for 2 book shops followed
by a grocery store. Now if we see a grocery store
first we simply ignore it (meaning that we stay in our
initial state), but seeing a book shop we will need to
remember that we have passed the first shop we
were looking for in that special sequence (meaning
that we change to a new state).
Designing a 110 Detector
(continued…)
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The same method can be applied to our problem,
where seeing a 0 is seeing a grocery store and a 1 is
a book shop. Thus as we saw above seeing a 0 first
must not change our state and so on. Applying this
method to our problem gives the following state
diagram:
1
0
a
0
0
1
1
b
0
c
d
0
1
0
1
0
Designing a 110 Detector
(continued…)
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In our flow of design the only part that doesn’t
actually involve mechanical steps is the drawing of
the problem’s state diagram. The rest that we see
next session is just a series of straight forward steps
that can be done by hand or using simulation tools.