Transcript CSE 431. Computer Architecture

OK, we are now ready to begin Chapter 2 of our text

We will begin looking at some preliminary stuff

Then we will look at the the Intel IA-32 (CISC)

Then we will concentrate on the MIPS 32 (RISC)
Note: A number of the slides I will use for Patterson
& Hennessy material are adapted, with permission,
from slides of a computer engineering colleague:
Professor Mary Jane Irwin of Penn State
Where is the Market?
Millions of Computers
1200
1122
1000
892
Embedded
Desktop
Servers
862
800
600
488
400 290
200
0
93
3
1998
114
3
1999
135
4
2000
129
4
2001
131
5
2002
ISA Type Sales
Other
SPARC
Hitachi SH
PowerPC
Motorola 68K
MIPS
IA-32
ARM
1400
Millions of Processor
1200
1000
800
600
400
200
0
1998
1999
2000
2001
2002
Moore’s Law


In 1965, Gordon Moore predicted that the number
of transistors that can be integrated on a die would
double every 18 to 24 months
(i.e., grow exponentially with time).
The million transistor/chip barrier was crossed in
the 1980’s.
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2300 transistors, 1 MHz clock (Intel 4004) - 1971
16 Million transistors (Ultra Sparc III)
42 Million transistors, 2 GHz clock (Intel Xeon) – 2001
55 Million transistors, 3 GHz, 130nm technology, 250mm2
die (Intel Pentium 4) - 2004
140 Million transistor (HP PA-8500)
Processor Performance Increase
Performance (SPEC Int)
10000
Intel Pentium 4/3000
DEC Alpha 21264A/667
DEC Alpha 21264/600
Intel Xeon/2000
1000
DEC Alpha 4/266
100
DEC AXP/500
DEC Alpha 5/500
DEC Alpha 5/300
IBM POWER 100
HP 9000/750
10
IBM RS6000
SUN-4/260
MIPS M2000
MIPS M/120
1
1987
1989
1991
1993
1995
Year
1997
1999
2001
2003
DRAM Capacity Growth
512M
256M
128M
1000000
64M
Kbit capacity
100000
16M
10000
4M
1M
1000
256K
64K
100
16K
10
1976 1978 1980 1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002
Year of introduction
Computer Instruction Formats

Three operand
e.g. Opcode Source1, Source2, Destination
 Two
operand
e.g. Opcode Source1, Source2Destination
One operand is used as Source & Destination
 One
operand
e.g. Opcode Source
Result is deposited in an Accumulator
The Intel IA 32
History of the IA-32 (Intel)
1971 – 4004 built by Intel as a calculator engine
1972 – 8008 introduced as an 8 bit computer
1974 – 8080 an 8 bit (16 address bit) enough power to build a computer
around it – Altair 8800, IMSAI 8080, Osborne I (first
portable computer 1981)
1976 – 8085 8080 with two interrupts
1978 – 8086 16 bit machine using enhanced 8080 instr & Reg
1980 - 8087 8086 floating pt co-processor
1981 - 8088 8 bit external data bus
1982 – 80186 & 80286 the later was the engine for the first IBM PC,
added memory management to become a multiuser machine
1985 – 80386 32 bit machine with 32 bit address space
1989 – 80486 multiprogramming, pseudo GPR machine
1992 – Pentium & Pentium Pro (1995) higher performance
1997 - Added MMX media extentions
1999 – Added another 70 instructions
Building a
legacy
nightmare !
2001 – Added another 144 instructions
2003 - Amdahl architecture increased address space to 64 bits and breaks legacy chain
2004 – Intel adopts AMD64 architecture with slight addition
IA-32 Registers
IA-32 Registers
IA-32 Flags Register
Example IA-32 Instruction Format
Sample IA-32 Instruction Formats
Note: Instruction lengths vary from 1 to 17 bytes
The MIPS 32
RISC - Reduced Instruction Set Computer

RISC philosophy (keep it simple!)






fixed instruction length(s) (one word?)
load-store instruction sets (don’t do anything else)
limited addressing modes
limited operations
MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC,
Intel (Compaq), Alpha, …
Instruction sets are measured by how well
compilers use them as opposed to how well assembly
language programmers use them
Design goals: speed, cost (design, fabrication, test,
packaging), size, power consumption, reliability,
memory space (embedded systems)
MIPS R3000 Instruction Set Architecture (ISA)

Registers
Instruction Categories




Computational
Load/Store
Jump and Branch
Floating Point
-


R0 - R31
coprocessor
PC
HI
Memory Management
Special
LO
3 Instruction Formats: all 32 bits wide
OP
rs
rt
OP
rs
rt
OP
rd
sa
immediate
jump target
funct
R format
I format
J format
MIPS Addressing Modes
1. Operand: Register addressing
op
rs
rt
rd
funct
Register
word operand
2. Operand: Base addressing
op
rs
rt
offset
Memory
word or byte operand
base register
3. Operand: Immediate addressing
op
rs
rt
operand
4. Instruction: PC-relative addressing
op
rs
rt
offset
Memory
branch destination instruction
Program Counter (PC)
5. Instruction: Pseudo-direct addressing
op
Memory
jump address
||
Program Counter (PC)
jump destination instruction
MIPS Register Convention
Name
Register
Number
$zero
0
$at
1
$v0 - $v1
2-3
$a0 - $a3
4-7
$t0 - $t7
8-15
$s0 - $s7
16-23
$t8 - $t9
24-25
$gp
28
$sp
29
$fp
30
$ra
31
Usage
Preserve
on call?
constant 0 (hardware)
n.a.
reserved for assembler
n.a.
returned values
no
arguments
yes
temporaries
no
saved values
yes
temporaries
no
global pointer
yes
stack pointer
yes
frame pointer
yes
return addr (hardware)
yes
MIPS 32 “Card”
MIPS Register File

Register File
Holds thirty-two 32-bit registers



Two read ports and
One write port
Registers are

Faster than main memory
src1 addr
src2 addr
dst addr
write data
32 bits
5
32 src1
data
5
5
32
32
locations
32 src2
- But register files with more locations
write control
are slower (e.g., a 64 word file could
be as much as 50% slower than a 32 word file)
- Read/write port increase impacts speed quadratically

Easier for a compiler to use
- e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs.
stack

Can hold variables so that
- code density improves (since register are named with fewer
bits than a memory location)
data
MIPS Organization
Processor
Memory
Register File
src1 addr
5
src2 addr
5
dst addr
write data
5
1…1100
src1
data
32
32
registers
($zero - $ra)
read/write
addr
src2
32 data
32
32
32 bits
branch offset
32
Fetch
PC = PC+4
Exec
32 Add
PC
32 Add
4
read data
32
32
32
write data
32
Decode
230
words
32
32 ALU
32
32
4
0
5
1
6
2
32 bits
byte address
(big Endian)
7
3
0…1100
0…1000
0…0100
0…0000
word address
(binary)