Transcript Lecture 1: Computer Architecture - College of Computing

Nanotechnology Stuff…
1
What I do.
Mike Niemier (a.k.a. Mike)
[email protected]
Phone: 404-894-1704 (w)
Phone: 404-843-9511 (h)
Georgia Institute of Technology
The College of Computing
Nanotechnology Stuff…
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My research goals…
• Introduce a systems-level research component to
computing at the nano-scale
– In my case with a device called “QCA”
• Advance coupling b/t nano-scale devices & computer
architecture
• Define operational regions for systems of QCA cells
• Combine advances in nano-scale devices and computer
architecture
– (to get to real systems sooner & more productively)
• Makes physicists work more with systems people
– Help them understand everything else that’s involved to
get to computation
– (and make them LIKE IT)
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Architects & nanotechnology
1st devices…
• Quantum transistors, RTDs, SETs, computing w/molecules, nanotube
arrays, quantum computing, DNA-based computation, …
Nano-tubes and Nano-wires:
(Fuhrer, Goldstein, Dehon)
• Applications
• Interconnect, SETs, levers
• Structures
• Arrays, crossbars, FPGAs, fabrics
• Challenges
• Alignment, defects, micro/nano
interfacing, gain/signal restoration
customization
• Hot: compile to space
• Not: compile to time
Quantum computing: (Oskin,
Chong, Chuang)
• Only small devices built, lots of error correction, dataflow?
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An intro. to QCA
• Conceptual Quantum-dot Cellular Automata (QCA)
– Binary information encoded in charge configuration
• A cell with 4 dots
• 2 extra electrons
• Tunneling between dots
Similar properties
cross implementation!
• Bi-stable, nonlinear
cell-to-cell response
• Restoration of signal
levels
• Robustness against
disorder
Cell-cell response function
Cell 1 Cell 2
Cell 1 Cell 2
• QCA, CMOS, and Zuse’s paradigm:
Paradigm shift
to molecular
electronics
QCA: molecules = charge containers, not current switches
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Why My Work (Part 1)
• CMOS provides faster devices, clocks, more
computation
– …but architects provide smarter computation
• Moore’s Law trends may be continued w/nano-scale
devices
– A particular focus: molecular nanoelectronics…
• High functional density: 1011-1013 devices/cm2 (ideally
1014)
• Ultimate limit of device scaling…
• Most nano-scale devices targeted for computational
systems
– Architects understand them best
– To complete the picture, we must answer:
• Can we “compute” within different device paradigms?
• Can system-level research help drive device research?
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Why my work? (part 2)
ISCA paper by topics
• ISCA: International Symposium
of Computer Architecture
– Only 2 papers on emergent
technologies to date…
• …but that session in 2001
• …and this work part of it
• Bob Colwell’s “3rd Prediction”:
– CMOS-based Moore’s Law ends
– Other technologies will be
looked at, needed; ISCA will
too
• NSF NIRT grantee conference:
– Question: “What’s missing?”
– Answer: “Architecture”
Source: Bob Colwell, ISCA 2002 keynote
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My Old Work
Early work:devices
Device physics work…
q1
ey
q2 = 0o
Design rules
bridge the gap
Molecular device
work
ey
1
1
4
3
3
1
1
2
3
2
3
4
1
Progressed to simple
circuits, architectures
2
3
4
5
6
A
B
C
D
E
F
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4
3
3
1
2
2
1
3
3
4
1
1
1
Custom work sets
the stage for
buildable designs
1
mP, generic architectures
next logical step
Algorithms to assist w/constraints
of QCA routing/layout
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A bit of background
Time
Step 1
Time
Step 2
Time
Step 3
Time
Step 4
Time
Time
Step 5
Fixed
“driver”
cell
“Schematic”
Switch
Relax
Release
Hold
Switch
Hold
Switch
Relax
Release
Hold
Release
Hold
Switch
Relax
Release
Relax
Release
Hold
Switch
Relax
Switch
Relax
Release
Hold
Switch
Clocking
Zone 1
Clocking
Zone 2
Clocking
Zone 3
Clocking
Zone 4
Clocking
Zone 5
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Wire Position
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Affecting device development
1
2
1
3
4
4
3
1
2
1
This floorplan
functionality seen
here…
Courtesy of Craig Lent
Device physicists/EEs studying how
to build/implement/test/simulate
our floorplan functionality
(input)
(input)
(device)
Logic on top
of wires
(output)
(input)
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A bit more of my old work
Instruction/
State
Read/Write
Acc
Read/Write
PC
Read/Write
IR
Bmuc
Select
New Mux
Select
B-Invert
(AND/OR)
Carry-in
Zero A
Logic /
Adder
Mem write
engable
PC/IR =
Mem. Add.
P+G+F+B+S+C
Hold
P+G+F+B+S
Hold
P+G
P
P+G+F
P+G+F
P+G+F
P+G+F
Disable
D.C.
M+H+E+N+G+F
+B+R+A
M+H+E+N+
G+F+B+R
Hold
Hold
M+H+E
+N+G
M+H+E+N
M+H+E+N
+G+F
M+H+E+
N+G+F
M+H+E+
N+G+F
M+H+E+
N+G+F
Disable
M
JMP
ADD
N
PC-to-Bmux feedback
Bmux select
J
Read/Write
ACC
B
R
B
Zero A
Logic/Adder
Read/Write
PC
S
Q
Memory
Instruction
Register
ALU
B-invert (AND/OR)
Carry-in
Program
Counter
Memory write
enable
D
PC/IR H
C
Select PC/IR as
memory addr.
M
K
Acc-to-memory feedback
E
Read/Write IR
A
Acc
F
P
A
L
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B Mux
Acc-to-ALU feedback
Memory-to-IR
(loads inst. into IR)
Now, coordinate
signal arrival times to
ensure processing will
occur at all
New
Mux
(loads PC for JMP)
Before: processing is
what’s possible in 1
time step
IR-to-ALU
G
I
Shows consequences
“pipelining provides”:
Computation ballistic!
Data from memory (for LOAD/arith. instruction)
(for STORE instruction)
IR-to-memory path
PC-to-memory path
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A roadmap for new work…
start
Gather basic
information – Ek,
required clock
strength, etc.
1
No
Can change
in clock help?
Yes
No
Can clock
be built?
Yes
10
Study race cond.,
calculate critical path
length
11
Design CMOS clock
structure to produce
E-field
Investigate thicker
wires, stronger clocks,
etc.
9
Yes
Yes
6
Do a logical circuit
layout in QCA
No
2
No
Simulate for logical
correctness
3
Are defects
tolerable?
Introduce defects into
logical layouts
(use stats from physical
experiments)
4
Re-simulate for logical
correctness
Is environmental
quality < Ek?
8
Is there
a “race”?
12
No
stop
Yes
Calculate # of cells
allowed per clock
window
7
5
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CAD
Duplicate to eliminate crosses
A
B
B
A
C
D
C
D
no crossing
eliminated
B
A
C
Rearrange to eliminate crosses
B
D
buildability
constraints met
by duplicating a
node
Minimize clock skew
Input A
x
Input B
Input C
Input
A
1
2
3
1
2
3
4
5
6
5
4
6
We can rearrange nodes to
eliminate crosses
Buildability Constraints
The building blocks that currently
make up our “parts library” are
restricted to the DNA-based
substrates (Fig. 9a), circuits that
use only 1 type of cell (i.e. only 90degree cells), and circuits that have
no wire crossings.
Logical crossings are also
possible…
Improve circuit density
A
B
y
Majority
Gate
Input
B
Window of
computation
CAD can address this problem by optimizing
for path length – or, as the clock moves
from left to right, reducing the vertical
height of wires (i.e. length x is shorter than
length y).
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B
xor
A
xor
A “logical” wire crossing
0 (and)
Input
C
Because of QCA’s clock, only certain # of
cells are active (able to compute) at any one
time. If it takes too long for a value to
propagate, the wrong answer will appear at
the output.
xor
A
M
B
M
1 (or)
M
0 (and)
This is the first cut of
an ALU; it is much less
dense than equivalent
designs.
XOR: (A and B’) or (A’ and B)
(there is an inherent crossing)
A
B
Using planar XOR made of NAND
gates, circuit at left can be built
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Systolic Architectures…
It’s also possible to design a similar circuit without the requirement that all signals
will have to arrive simultaneously. This circuit is shown below. This circuit will take
longer to process the output. Also, x values will have to be asserted for two clock
cycles as opposed to 1. Thus, an input pattern would be x1, x1, x2, x2, x3, x3, …
Aout
xin
Ay
w3 = 1
Bout
w2 = 0
Ax
Ay Bout
w3=1
Ax
xin
A
Cout
Cy
Bx
Bx
B
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Xin
Yin
W
Xout
C
By Cout
w2=0
Yout
based on…
w1 = 1
B
A
Aout
By
Cy
w1=1
Cx
C
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Systolic Processing (and errors)
Sources of error
a
b
….
a
b
c
d
d
e
Possible sources of error in systems of
molecular QCA cells. Missing cells (a), wrong
distance between cells (b), offcenter cells (c),
rotated cells (d), and offcenter cells in the
“y”-dimension (e).
c
The QCA circuit in terms of
logic gates
The top part of this figure shows a DNA tile with four schematic QCA molecules
attached to specific sites in the major groove of one DNA helix (a). This DNA tile
is one of nine tiles which would form a diamond-shaped raft 60 nm long by 12 nm
wide. After ligation to prevent disassembly, six of these rafts would assemble (b)
into a functional pattern matching circuit in an area of less than 0.01 square microns.
Part (c) shows how the DNA circuit board could self-assemble on a surface with
buried clocking wires; the wires are about 25 nm in diameter on a 75 nm pitch. This
circuit would be capable of matching a specific string of 1s and 0s to an input stream
of 1s and 0s – hardware that could be used in internet search engines to locate items
in a database, to find an address in a computer’s memory, etc.
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w2(0)
w3(1)
xin
xout
xin
xout
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Detailed design rules
Rule 2B: Disorder
How is disorder affected by Ekink?
2B
r
ndisordered = # cells
ndisordered = # cells
q
Ekink ~ (1/r5)(cos4q ).
As q increases, Ekink decreases.
q1
q 2 = 0o
Ekink ~ (1/r5)(cos2(q1+ q2)).
As q1 or q2 increases, Ekink decreases.
Why they are important:
• Successful binary value transmission dependent on no external energy
greater than the smallest kink energy
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Me
• Name:
– Michael Niemier (a.k.a. “Mike”)
• Contact:
– E-mail: [email protected]
– Phone: (404) 894-1704
– My office: 219
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End of talk…
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