Transcript Poster_TWEPP_mattiazzo

S. Mattiazzo1,2, M. Battaglia3,4, D. Bisello1,2, D. Contarato4, P. Denes4, P. Giubilato1,2,4, D. Pantano1,2, N. Pozzobon1,2, M. Tessaro2, J. Wyss2,5
1
Dipartimento di Fisica, Università degli Studi di Padova, I-35131 Padova, Italy; 2 Istituto Nazionale di Fisica Nucleare, Sezione di Padova, I-35131 Padova, Italy; 3 Department of Physics, University of California, Berkeley, CA 94720, USA;
4 Lawrence Berkeley National Laboratory, Berkeley, CA 94720, USA; 5 DiMSAT, Università degli Studi di Cassino, Cassino, Italy.
Monolithic pixel detectors in 0.20µm Silicon On Insulator (SOI) technology have been developed, realized and characterized.
This work shows the decisive effect of the substrate bias condition during irradiation on the total dose damage of the electronics.
SOI technology for monolithic pixel sensors:
Chip production:
In the SOI technology CMOS electronics is implanted on a thin silicon layer on top of a buried oxide (BOX): this
ensures full dielectric isolation, small active volume and low junction capacitance (higher latch-up immunity, lower power
consumption, higher speed applications)
OKI (Japan) provides 0.15µm and 0.20µm Fully Depleted (FD) SOI
processes with high-resistivity substrate (700 ·cm) and vias etched through
the oxide which contact the substrate from the electronics layer, so that pixel
implants can be created and a reverse bias can be applied.
SOI-1
(2007)
[Y. Arai, KEK]
Fractional Yield:
• 0.20µm OKI FD-SOI technology
• 256256 analog pixels (13.7513.75µm2)
• 4 analog outputs
• 5mm chip, 3.2mm active
• Just delivered
• 0.20µm OKI FD-SOI technology
• 128172 digital pixels (2020µm2)
• 40172 analog pixels (2020µm2)
• Optimized for low leakage current
• Currently under test
• 0.15µm OKI FD-SOI technology
• 16050 digital pixels (1010µm2)
• 160100 analog pixels (1010µm2)
• MIPs detection
• First radiation damage tests
Only results on 0.20µm process are shown in the poster, as this process is
optimized for low leakage currents and will be used for the development of
future detectors.
SOI-2-IMAGER
(2009)
SOI-2
(2008)
Total dose tests:
When exposed to ionizing radiation, electron-hole pairs are created inside
the thick oxide.
The X-ray irradiation facility installed at the INFN National Laboratory of Legnaro (Padova, Italy) and used for the total dose
damage studies described in this poster is the Seifert Rp-149 Semiconductor Irradiation System
Test structures:
X-ray machine:
If a depletion voltage is applied to the detector (substrate), a strong
electrical field is present inside the BOX.
OKI 0.20µm FD process
16 NMOS and 16 PMOS transistors with source in common, gate
and drain separated
Each transistor is surrounded by 1µm PSUB guard ring
Both Body floating and Body Tie transistors
W/L = 500
Normal, Low, High Voltage Threshold
Tube with W (7.4-12.06 keV L-lines) anode.
Maximum tube voltage 60 kV. Maximum tube current 50
mA.
X,Y (motorized) and Z (manual) axis for accurate
position setting of the tube.
Irradiation in air at room temperature.
Dose rate: 165rad(SiO2)/sec.
Due to the presence of the electrical field, charges are immediately
separated and do not recombine.
The electron-hole pairs escaping recombination (fractional yield) lead
to positive charge trapping throughout the BOX and consequently to an
increase of the top-gate leakage current.
Bias
conditions
during
irradiation:
THE TOTAL DOSE DAMAGE ON THE TRANSISTOR
STRONGLY DEPENDS ON THE BIAS GIVEN TO THE
SUBSTRATE DURING IRRADIATION
 NMOS and PMOS Body of Body Tie transistors at 0V.
 Drain and source at 0V, gate NMOS HIGH (1.8V), gate PMOS LOW (0V).
 Substrate bias voltage (Vback) :
Vback = 0V, 5V, 10V with PSUB guard-ring floating
 Vback = 10V with PSUB guard-ring at 0V
(is the PSUB guard-ring effective in containing the electrical field
through the BOX?).
NMOS transistor: (L = 0.50µm, W = 250µm, Normal Vthr, Core transistor, Body Tie) for four different bias conditions:
1.E-04
60 krad
100 krad
1.E-06
300 krad
1.E-08
1.1 Mrad
1.E-12
-0.2
2 Mrad
0.2
0.6
1
1.4
18 krad
23 krad
1.E-04
28 krad
30 krad
1.E-06
56 krad
1.E-08
1.E-12
-0.2
0.2
0.6
Vgs (V)
Vgs (V)
1
1.4
33 krad
1.E-06
48 krad
100 krad
1.E-10
160 krad
1.E-12
-0.2
1.8
B or P(~5·1015cm-2)
43 krad
1.E-08
70 krad
1.E-10
1.8
1.E-02
1.E-04
680 krad
1.E-10
16 krad
1.E-02
PSUB
GUARD-RING
55 krad
BOX
62 krad
0.2
0.6
Vgs (V)
1
1.4
SOI
electronic layer
1.E+01
pre
1.E-01
18 krad
1.E-03
28 krad
1.E-05
38 krad
1.E-07
68 krad
1.E-09
88 krad
1.E-11
128 krad
1.E-13
-0.2
208 krad
1.8
0.2
0.6
PSUB
guard-ring
The PSUB guard-ring is effective in limiting the backgate effect
1.4
1.E-02
1.E+00
1.2
1.E-04
Vthr (V)
Ileak (A)
1.E-06
1.E-07
0.8
1.E-02
Vback = 2V
1.E-02
1.E-04
Vback = 4V
1.E-04
1.E-06
Vback = 6V
0.6
1.E-10
Vback = 12V
1.E-10
1.E-12
-0.2
Vback = 15V
1.E-12
-0.2
0.4
1.E-09
1.E-10
10V (PSUB
guard @ GND)
1.E-11
1.E+03
10V (PSUB
guard @ GND)
0.2
0
1.E+00
1.E+01
1.E+04
1.E+02
1.E+03
1.E-08
Vback = 10V
10V
0.2
0.6
1
1.4
Vback = 0V
Vback = 2V
Vback = 4V
Vback = 6V
Vback = 8V
Vback = 10V
Vback = 12V
Vback = 15V
1.E-06
Vback = 8V
1.E-08
10V
1.E-08
Ids (A)
5V
5V
1.E+00
Vback = 0V
1
1.E-05
PSUB guard-ring “floating”
PSUB guard-ring at GND
0V
0V
1.E-03
1.E+02
1.8
Threshold Voltage
Leakage current
1.E+01
1.4
Vgs (V)
The leakage current and the threshold voltage strongly depend on the bias condition during
irradiation: the higher Vback, the higher Ileak and the lower the Vthr (greater damage on the BOX).
1.E-12
1.E+00
1
The PSUB guard-ring
tied at GND during
irradiation indeed limits
the electrical field
through the BOX and
improves the radiation
hardness of the device.
Ids (A)
30 krad
pre
pre
Vback = 10V
(PSUB guard-ring @ GND)
Ids (A)
1.E-02
1.E+00
1.E+00
Ids (A)
pre
Ids (A)
Ids (A)
1.E+00
Vback = 10V
(PSUB guard-ring Floating)
Vback = 5V
(PSUB guard-ring Floating)
Vback = 0V
(PSUB guard-ring Floating)
1.8
0.2
0.6
1
1.4
1.8
Vgs (V)
Vgs (V)
1.E+04
Dose (krad)
Dose (krad)
C-V measure on SOI-2 chip:
For Vback = 0V the transistor is still working properly up to doses of ~1Mrad.
Expected curve
(depletion increase)
Vback
[Toshinobu Miyoshi (KEK) presented at STD7, Hiroshima, 2009]
B
BURIED
P-WELL
(BPW)
(~1·1012cm-2)
SOI
electronics
layer
BOX
pixel
Vback
[Toshinobu Miyoshi (KEK), presented at STD7, Hiroshima, 2009]
Conclusions and future studies:
We verified the dependence of the total dose damage from the substrate bias condition during irradiation;
This work was supported by the Director, Office
of Science, of the U.S. Department of Energy
under Contract no. DE-AC02-05CH11231 and
by INFN and University of Padova, Italy.
We are also grateful to Prof. Yasuo Arai (KEK)
for the effective collaboration in the
development of SOI pixel detectors and for
providing us with the test structures.
With the BPW, no
back gate effect up
to 80V (~60µm).
A lower electric
field in the BOX
should also improve
radiation hardness
peripheral
Buried P-Well (BPW)
Acknowledgements:
IR laser test on intpix3 (same pixel as intpix2)
200
180
160
140
120
100
80
60
40
20
0
Calculated
Measured
0
20
40
60
80
100
120
Vback (V)
References:
•
Y. Arai et al., Proceedings of SNIC Symposium, 2006.
•
M. Battaglia et al., Nuclear Instruments and Methods in Physics Research A, Vol.
583, Issues 2-3, 21 December 2007, p. 526-528. arXiv:0709.4218 [physics.ins-det]
•
M. Battaglia et al., Nuclear Instruments and Methods in Physics Research A, Vol.
604, Issues 1-2, 1 June 2009, p. 380-384. arXiv:0811.4540 [physics.ins-det]
•
M. Battaglia et al., M. Battaglia et al., Journal of Instrumentation (2009).
arXiv:0903.3205 [physics.ins-det]
•
D. Bisello et al. Radiation Physics and Chemistry 71, 713 (2004).
•
Y. Arai talk at STD7, Hiroshima, September 2009.
A low electrical field through the BOX would allow the transistors to work properly up to doses of ~ 1Mrad
Both the backgate effect and the radiation sensitivity would improve, provided a method to keep low the potential under
the BOX. Different solutions should be investigated:
a different geometry of PSUB guard-ring implantation on the substrate
a buried P-Well under the BOX in the next version of the SOI-2-imager
Depletion depth
W ( mm)
Back gate effect
With a standard PSUB
implantation,
for Vback > 10V, output
starts decreasing due to
back gate effect
A new implant method was provided by OKI in
2008, consisting of a lightly doped P-well implanted
below the BOX through the SOI layer.
(700·cm is the nominal resistivity)
ADC OUT [ADU]
ADC OUT [ADU]
IR laser test on intpix2
measured depletion is smaller than expected