Transcript presentation

Electronics for PS and
LHC transformers
Grzegorz Kasprowicz
Supervisor: David Belohrad
AB-BDI-PI
Technical student report
Why new PS transformers
electronics is needed?
 Current
calibration procedure doesn't
allow full scale calibration on the low
sensitivity range -> source of error
 It does not support remote
adjustments (required by LHC)
 Calibrators work only in manual
mode – require operator in place
they are installed during calibration
procedure
PS integrators – following
conceptions were built and
tested
 Analogue
integrator solution based
on diode switches and high speed
OPAMPs
 Analogue integrator solution based
on IVC102U integrated chip
 Digital solution based on High Speed
ADCs
Analogue integrators prototype
board
Analogue integrator 1
 This
version was implemented using
diode switches driven by current
switches.
 The linearization block that
compensates diode switches
nonlinearities was used
 High speed voltage feedback opamps
were used
 Linearity results meet PS needs
Integrator 1 linearity results
error vs input current
0.8
0.6
0.4
error[%]
0.2
Series1
0
-6
-5.5
-5
-4.5
-4
-3.5
-3
-2.5
-2
-1.5
-1
-0.5
-0.2
-0.4
-0.6
current [mA]
0
0.5
1
1.5
2
2.5
3
3.5
4
Analogue integrator 2
 Based
on IVC102U chip, which
integrates operational amplifier,
switches and capacitors.
 Too slow for PS application –
minimum integration time is ~30us
while 5us is needed – it saturates
output when clocked too fast.
Digital integrator
Existing project PCBs (CCD camera) were
used. It consists of: FPGA, 8051
microcontroller with USB 2.0 interface,
SDRAM memory, power supply, 2x 12bit
210MS/s ADC, configuration and program
EEPROM, input amplifiers.
 The input signal is sampled and integral
over specified period is calculated digitally
in FPGA. Then the result is stored in RAM
and transferred to PC via USB

Digital integrator prototype board
- existing project was used
USB+
8051
2x ADC
12bits
210MHz
Program
EEPROM
USB
Connector
FPGA
Digital integrator – linearity
results
linearity error vs input curent
0.2
0.1
Error [%]
-0.1
-0.2
-0.3
-0.4
-0.5
Input current [uA]
10
00
11
00
12
00
13
00
90
0
80
0
60
0
70
0
50
0
30
0
40
0
20
0
0
10
0
-9
00
-8
00
-7
00
-6
00
-5
00
-4
00
-3
00
-2
00
-1
00
00
0
10
0
-1
20
0
-1
-1
-1
30
0
0
Digital Integrator
 Linearity
measured meets PS
requirements, but there is expected
further improvement caused by
proper clocking and noise.
 This version was chosen to
realization as final prototype due to
it’s simplicity, reliability and
measurement parameters.
Digital integrator - advantages
 No
precision analog components
required, only input amplifier, Low
Pass Filter and ADC driver
 Linearity guaranteed by ADC
 Good thermal stability
 Simplicity – fewer component count
that improves reliability
 Thanks to FPGA, function of device
can be changed remotely
Linearity measurement test bench
 Integrators
1 and 2 were connected
to digital integrator board to simplify
measurements
 Simple control application working
under Windows was written to allow
easy control of integrators
parameters and results acquisition
Testbench
Control application
PS Calibrators – following
conceptions were built and tested
 Charge
calibrator with 200V DC/DC
converter
 Current
calibrator – switched current
source 4A/200V
PS charge calibrator
 How
does it work?
 Disadvantages
 Newer version of existing calibrator –
instead of mechanical switch,
MOSFET was used. This allows
remote operation
 Integrated 12V/300V DC/DC
converter that simplifies supply
Charge calibrator prototype
PS current calibrator
How does it work?
 Disadvantages
 There was built adjustable pulse current
source – 0..4A / 50 Ohm
 Switch on/off time <100ns
 Problems with thermal stability, linearity
and transients occurred – improved
solution with compensation was developed
 Prototype was built using discrete
components (transistors only), improved
version uses CFA and MOS drivers

PS current calibrator
VME Intensity measurement system
for PS
Compact single board solution based on VME bus
 Integrated current/charge calibrator
 Integrated HV DC/DC converter
 Based on FPGA technology ensures high flexibility
 Two high speed ADCs working in parallel
 System can be used for another data acquisition
applications
 All functions and adjustments controlled remotely:
- Integration delay, gate time
- calibration delay, pulse width, gate time & delay
- offset compensation gate& delay, analogue
compensation
- calibrators voltage and current
- ….

VME board block schematic
ADC 12bit
210Ms/s
VME BUFFERS
FPGA
ADC 12bit
210Ms/s
Power
Supply
1.5V
2.5V
3.3V
5V
-5V
programmable
DC/DC
12V/200V
converter
Input Filter
And
Attenuator
Current calibrator –
Programmable pulse current
Source – 0..4A,max 200V
Charge calibrator
Switched capacitor
OUT I
OUT Q
IN
VME integrator parameters
VME 32bit interface
 FPGA 6k Logic Elements
 2xADC 12 bit,210Ms/s with LVDS
 All VME signals are buffered
 HV DC/DC converter 0..200V programmable
range with output voltage monitor
 Pulse current source 0..4A programmable
range
 10.5 ENOB with 50 Ohm input short
 Linearity better than 0.2%
 Offset compensation (analog and digital)

VME integrator - prototype
DC/DC
converter
2x ADC
12bit,210MS
Calibrators
LPF
FPGA
Supply
regulators
Bus
buffers
VME board – final version
VME measurement system status
 The
new board is assembled and
soon will be ready for tests
 The single test software running on
VME controller is written
 The software group (M.Ludwig,
J.J.Gras) is working on drivers
VME board – final version
 Ready-made
PCB shielding used
 Compensated current calibrator
 Current feedback controller in DC/DC
converter
 Test outputs on the front panel
 Status LEDs on the front panel
 Polymer fuses added
 Board address selection switch
 Fixed minor bugs
Fast integrator for LHC
 Existing
integrated (LHC-2002)
requires using 2 or more channels to
achieve 30dB of dynamic range. The
improvement of dynamic range gives
the possibility to use one
measurement range only
 Low input voltage range
 Too high input voltage causes chip
damage
 There is under development discrete
solution
Fast integrator for LHC – version 1
Based on diode switches driven by
transformers
 2 versions of diode drivers built and tested
(integrated and discrete one)
 High speed VFA and CFA tested –
problems with stability occurred
 Discrete version of CFA developed –
problem with output range and power
dissipation of used transistors
 Problem with too high reset time

Fast integrator for LHC – version 1
Fast integrator for LHC – version 2
 Solved
problem with power limitation
of transistors and output voltage
range
 Still too high reset time (ECL logic
used)
 Diodes replaced by MOSFET
 SRD solves problems with reset time
– still under development
Fast integrator for LHC –
version 2 - block schematic
IN
OUT
Current
follower
Pulse
trafo
CLK
ECL timing
Fast integrator for LHC – version 2
Fast integrator for LHC – version 3
LHC integrator testbench
 Based
on Cyclone FPGA
Development KIT
 Small mezzanine module was
developed
 14bit, 60MS ADC + drivers
 It was used to measure integrator’s
linearity
LHC integrator testbench
LHC integrator linerity
integrator error [%] vs input voltage
0.5
0
count
-0.5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-1
Series1
-1.5
-2
-2.5
-3
input voltage
Generator amplitude error [%] vs output voltage
0.5
count
0
-0.5
1
2
3
4
5
6
7
-1
8
9
10
Series1
-1.5
-2
-2.5
output voltage
The following projects are currently
under development
 VME
Intensity measurement system
for PS
 Fast integrator for LHC (alternative
for existing integrated solution)