Transcript Trigger System

Status of the electronics systems
of the MEG experiment
PSI - Jun. 27th, 2006
1
Electronic chain
HV
front PMT
216
Active
Splitter
1:1
1:1
4:1
lateral PMT
630
Active
Splitter
1:1
1:1
4:1
Active
Splitter
1:1
1:1
4:1
LXe
HV
60
bars PMT
TC
Ramp
Pre-Amp
DRS
DRS
DRS
DRS
DRS
DRS
8:1
512
HV
Wires
Pre-Amp
Strips
Pre-Amp
PSI - Jun. 27th, 2006
Trigger
Trigger
Trigger
3 crates
HV
fibers APD
DC
120
atten
5 crates
32
576
1156
Aux. devices
Hit
registers
4 boards
2
DAQ and control
pE5 area
‘counting room’
Trigger
clock
start
stop
sync
Ancillary
system
Trigger
Trigger
Trigger
3 crates
Busy
Error
Run start
Run stop
Trigger config
DRS
DRS
DRS
DRS
DRS
DRS
20 MHz
clock
Hit
registers
6 crates
PSI - Jun. 27th, 2006
Front-End PCs
Main DAQ PC
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Gigabit
Ethernet
PC (Linux)
PC (Linux)
PC (Linux)
PC (Linux)
Trigger signal
Event number
Trigger type
storage
Event
builder
On-line farm
3
HV
PSI - Jun. 27th, 2006
4
HV
Active down regulation of an
external HV supply
PSI design
• 10 chn per board
• 180 chn per 3 HE crate
• Back side connector
• Total of 6 crates
4 different requirements:
–
–
–
–
Lxe: 1000V , 100 uA
TC bars: 2400V, 1 mA
TC curved: 500V, <1 uA
DC: 2400V, ~1 uA
Commercial HV supplies delivered
Mass production in progress
Installation in September
PSI - Jun. 27th, 2006
5
Splitters
PSI - Jun. 27th, 2006
6
Splitter layout
•
ERNI high bandwidth
output connector
•
crosstalk with ERNI
connector plus 2m
cable is ~ 0.6%
Trigger
or DRS
DRS
Trigger
PSI - Jun. 27th, 2006
Input
Power
7
Backplane layout
• Test circuit was implemented on backplane
• Debug completed
• PCB production in progress, mounting in house
PSI - Jun. 27th, 2006
8
Crates
• Mechanic parts and fans delivered
• Power supplies delivered and tested
Frontal panel
Back panel
PSI - Jun. 27th, 2006
Output (5V-36A)
9
Cables
Inputs
• Single coaxial cable (RG178 – 9m long)
bundled into a polyester braided sleeve
• Negligible crosstalk between cables.
DRS outputs
• High bandwidth output (DRS)
•
high density twisted pairs cable (0.68 pitch)
2 m long with one flat zone in the middle
(Amphenol SPECTRASTRIP 68p)
Trigger outputs
– Low density twisted pairs cable (1.27
pitch) 2 m long with 2 flat zone (3M
34p/10p)
PSI - Jun. 27th, 2006
10
Splitter
–
–
–
–
–
–
–
Splitter Summary
first prototype finished in may successfully
PCB production started the first of June
PCB production time one month
Component procurement in progress
Board mounting 2 weeks end of July
Board test 1 week
Boards ready by the beginning of September
Backplane
– Crates and power supply delivered
– backplane production in Lecce
Cables
– Trigger cables ready
– LXe cables in production
– DRS cables in production
Installation
– Foreseen between September 5 and 20
PSI - Jun. 27th, 2006
11
TC
PSI - Jun. 27th, 2006
12
PMT ramp generator
B
to Splitter
Analog signals
to DRS and trigger
PMT
S
B
TC Analog Sign. Monitor
Passive
Splitter
6U Eurocards
boards
8 boards
PSI - Jun. 27th, 2006
D/D
RAMP
GEN.
to Splitters
Signals to DRS
Dual Threshold OR
Constant Fraction OR
Leading edge
discriminator
NIM Signal
13
for any possible use
Production
PMT ramp generator
• Design of the final boards in progress
• Mass production September (?)
• system delivery 8 boards October (?)
APD pre amplifiers
• First prototype with problems on IC and cross talk
• Second prototype design and test completed
•
•
Mass production and test in progress
system delivery end of July
APD hit registers
• board design completed
• Production and test in progress
• system delivery (6 boards – 6U VME) end of July
PSI - Jun. 27th, 2006
14
Trigger
PSI - Jun. 27th, 2006
15
Front end
Type1
PSI - Jun. 27th, 2006
Trigger
Boards
Type2
Ancill
16
System
test
4 Type1
2 Type2
2 Ancillary
• Synchronous
operation
• No transmission
errors
PSI - Jun. 27th, 2006
17
Splitter-Type1
connection
PSI - Jun. 27th, 2006
Alpha and cosmic muon events
from the Pisa facility
18
Number of boards: summary table
PMT
LXe
col
tot
inner
9
24
216
1
14
1
up
9
6
54
4
1
1
down
9
6
54
4
1
1
lateral
6
24
144
4
lateral
6
24
144
4
5
1
back
9
24
234
4
4
1
846
25
15
2
30
1
2
1
TC d.s.
15
2
30
1
2
1
2
512
8
4
1
TC curved 256
572
n.
Connections
board
Type2-Type2
Type2
2
1
1
2
8
1
1
16
16
256
8
2
1
aux dev
16
1
16
1
1
1
TOTAL mounted
36
4
Spare fraction
0.35
0.55
49
8
PSI - Jun. 27th, 2006
1
1
wires
TOTAL produced
n.
board
Type2
3
TC u.s.
Total
DC
n.
Connections
fanin board
Type1-Type2
Type1
row
Total
TC
Number of trigger boards
1
19
Number of boards: status
Boards Type1
•
•
•
•
•
48 funded
36 needed
40 delivered
8 not completely mounted
40 tested
Front-End Boards
•
•
•
•
800 funded
576 needed
800 delivered
320 tested
PSI - Jun. 27th, 2006
Boards Type2
•
•
•
•
10 funded
5 needed
10 delivered
10 tested
Boards Ancill
•
•
•
•
•
8 funded
4 needed
4 delivered
4 not completely mounted
2 tested
20
Firmware V1.0 Present Status
Type1 :
• Type1-0
• Type1-1
• Type1-2
• Type1-3
VIRTEX II- PRO (XC2VP20-7-FF1152) 
LXe front face 
LXe lateral faces 
LXe top,bottom and back face 
TC bars 
• Type1-4
TC fibers 
• Type1-5
DC 
• Type1-6
• Type1-7
Auxiliary devices 
LXe back face x
Type2 :
• Type2-0
VIRTEX II- PRO (XC2VP40-7-FF1152) 
Final Level completed 
• Type2-1
LXe front+up/down faces 
• Type2-2
LXe lateral faces 
• Type2-3
TC 
PSI - Jun. 27th, 2006
21
Board Type3
PSI - Jun. 27th, 2006
22
Board Type3
Modified Type1 boards to produce an auxiliary
digitization of the LXe signals
•
•
•
•
•
•
•
•
Type3 board 32 channels
Number of boards for the LXe lateral sides(612 chn): 20
Boards design : ~ ready
PCB prototype : end of July
Component delivery: (12 weeks) ~ beginning of September
Test: September
Production: October
Installation: end of October
PSI - Jun. 27th, 2006
23
Comments on trigger
Installation
-
Ready: any time from beginning of Jul. to end of Aug.
Should follow the NaI moving system
Should precede the electronic integration Sep.
DAQ computers
Configuration
- Baseline version V1.0 written
- Needs tuning, at least 1 month during purification
- Needs analysis tools, under development
Documentation
- Hardware register list available
- Almost available for Type1
- In progress for Type2
PSI - Jun. 27th, 2006
24
DRS
PSI - Jun. 27th, 2006
25
DRS
• DRS2 available for all channels
• New PMC card finished
–
–
–
–
Reduced noise 1.2 mV → 0.5 mV RMS
Self-calibration on card
Mass production started
cards expected in August
• PSI GPVME boards in production
– Delivery end of August
PSI - Jun. 27th, 2006
26
DRS2 issues
Issue
Solution
Voltage nonlinearity
Calibration with cubic splines in Front-end

Clock nonlinearity
Time calibration & frequency regulation

Cross talk
1% @ 7ns risetime
Redesign of CMC card with ERNI 68-pin
connector and interleaved ground lines

Temperature
dependence
- Calibration maybe possible to some extend
- Keep electronics temperature constant
- On-chip temperature compensation
?
()
- Only use small signals (<0.5 V)
- On-chip temperature compensation
()
Self-heating of cells
Ghost pulses
DRS2
- Veto trigger ~5us after cosmic or LED event
- Veto trigger after other calorimeter hits?
- Record 2us calorimeter history in each event?
- Redesign sampling cell
DRS3



?
?

All issues could be resolved as planned
PSI - Jun. 27th, 2006
27
DRS3
• DRS3 design finished
• Prototypes expected in August
• Tests foreseen at the end of the year
PSI - Jun. 27th, 2006
28
DRS3 layout
• Smaller “standard cells”
• Totally > 600,000
transistors
• Smaller package (QFP64)
• 12 channels/chip
• ROI readout and parallel
readout to reduced
dead time:
230 ms → 50 ms → 5 ms
PSI - Jun. 27th, 2006
29
DRS and Trigger Crates
20 cm
Power distribution box
PSI - Jun. 27th, 2006
Issue: “Splitter” rack cannot be
accessed easily from back side!
30
DAQ cluster
PSI - Jun. 27th, 2006
31
DAQ Cluster Layout
80 GB System Disk
RAID 1 (Mirror)
VME-Interface
Front-End #1
80 GB System Disk
RAID 1 (Mirror)
VME-Interface
Front-End #2
NFS
...
80 GB System Disk
RAID 1 (Mirror)
1.2 TG Data Disk
RAID 5
/home/meg
PSI - Jun. 27th, 2006
SC-FE
/home/meg
|-|-|-|-`--
root
<- ROOTSYS
midas
<- MIDASSYS
mxml
rome
<- ROMESYS
meg
<- MEGSYS
|-- meganalyzer
|-- megbartender
|-- megmc
`-- online
|-- drivers
|-- eventbuilder
|-- frontend
|-- slowcontrol
|
|-- bts
|
|-- calorimeter
|
`-- scfe
|-- trigger
`-- VPC
Back-End
Data rate
100 MB/s
32
Front-end computers
GBit Switch
Front-end #1
• Two DAQ computer installed
with DAQ software
• Remaining computers delivered
• Installation end of July
PSI - Jun. 27th, 2006
Back-end
1.2 TB disk
33
Offline Cluster
15 x 500 GB SATA
GBit Ethernet
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
Fiber Channel Switch
Sun Fire x4100 quad core 4 GB
Sun Fire x4100 quad core 4 GB
•
•
•
•
PSI - Jun. 27th, 2006
Ordered on June 14th: 20 cores + 30 TB disk
Easily extensible
Redundancy through GFS/GPFS file systems
GBit link to online cluster requested
34
Slow control
PSI - Jun. 27th, 2006
35
SCS-2000
• Replaces SCS-1001 unit
• 64 I/O lines (analog, digital,
opto-coupler, PT100, etc.)
• Outputs stable during CPU
firmware upgrade (→ BTS
control)
• “Soft” fuse
• LED pulser (40 lines, computer
controllable)
PSI - Jun. 27th, 2006
36
BTS slowcontrol
• Slowcontrol back-end to
MSCB slow control units
• Integrated in MIDAS
history system
• Monitoring and control
though MIDAS web
pages
• More pages added as SC
equipment gets
operational
PSI - Jun. 27th, 2006
37
MIDAS history
PSI - Jun. 27th, 2006
38
Conclusions
• All the key elements of the electronic system are
available for integration in September
• Some parts will arrive with ~1 month delay
PSI - Jun. 27th, 2006
39
Rack space
PSI - Jun. 27th, 2006
40