Transcript CPE 432 Computer Design - 10

CPE 432 Computer Design
10 – Limits to ILP
Dr. Gheith Abandah
Adapted from the slides of Prof. David Patterson, University of
California, Berkeley
Limits to ILP
• Conflicting studies of amount
– Benchmarks (vectorized Fortran FP vs. integer C programs)
– Hardware sophistication
– Compiler sophistication
• How much ILP is available using existing
mechanisms with increasing HW budgets?
• Do we need to invent new HW/SW
mechanisms to keep on processor
performance curve?
–
–
–
–
Intel MMX, SSE (Streaming SIMD Extensions): 64 bit ints
Intel SSE2: 128 bit, including 2 64-bit Fl. Pt. per clock
Motorola AltaVec: 128 bit ints and FPs
Supersparc Multimedia ops, etc.
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CPE 432, 10-ILP Limits
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Overcoming Limits
• Advances in compiler technology +
significantly new and different hardware
techniques may be able to overcome
limitations assumed in studies
• However, unlikely such advances when
coupled with realistic hardware will
overcome these limits in near future
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Limits to ILP
Initial HW Model here; MIPS compilers.
Assumptions for ideal/perfect machine to start:
1. Register renaming – infinite virtual registers
=> all register WAW & WAR hazards are avoided
2. Branch prediction – perfect; no mispredictions
3. Jump prediction – all jumps perfectly predicted
(returns, case statements)
2 & 3  no control dependencies; perfect speculation
& an unbounded buffer of instructions available
4. Memory-address alias analysis – addresses known
& a load can be moved before a store provided
addresses not equal; 1&4 eliminates all but RAW
Also: perfect caches; 1 cycle latency for all instructions
(FP *,/); unlimited instructions issued/clock cycle;
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Limits to ILP HW Model comparison
Model
Power 5
Instructions Issued
per clock
Instruction Window
Size
Renaming
Registers
Branch Prediction
Infinite
4
Infinite
200
Infinite
Cache
Perfect
Memory Alias
Analysis
Perfect
48 integer +
40 Fl. Pt.
2% to 6%
misprediction
(Tournament
Branch Predictor)
64KI, 32KD, 1.92MB
L2, 36 MB L3
??
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Perfect
CPE 432, 10-ILP Limits
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Upper Limit to ILP: Ideal Machine
160
FP: 75 - 150
150.1
140
Instruction Issues per cycle
Instructions Per Clock
(Figure 3.1)
120
Integer: 18 - 60
118.7
100
75.2
80
62.6
60
54.8
40
17.9
20
0
gcc
espresso
li
fpppp
Programs
doducd
tomcatv
6
Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions Infinite
Issued per
clock
Instruction
Infinite, 2K, 512,
Window Size 128, 32
Infinite
4
Infinite
200
Renaming
Registers
Infinite
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Perfect
Perfect
Cache
Perfect
Perfect
Memory
Alias
7/21/2015
Perfect
Perfect
2% to 6%
misprediction
(Tournament Branch
Predictor)
64KI, 32KD, 1.92MB
L2, 36 MB L3
??
CPE 432, 10-ILP Limits
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More Realistic HW: Window Impact
Figure 3.2
Change from Infinite
window 2048, 512, 128, 32
FP: 9 - 150
160
150
IPC
Instructions Per Clock
140
119
120
Integer: 8 - 63
100
75
80
63
60
40
20
61
55
60
59
49
36
1010 8
41
45
34
35
1513
8
1815
1211 9
1615
14
14
9
0
gcc
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espresso
li
f pppp
Inf inite
2048
512
CPE 432, 10-ILP Limits
128
doduc
32
tomcatv
8
Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions 64
Issued per
clock
Instruction
2048
Window Size
Infinite
4
Infinite
200
Renaming
Registers
Infinite
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Perfect vs. 8K
Tournament vs.
512 2-bit vs.
profile vs. none
Perfect
Cache
Perfect
Perfect
Memory
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Alias
Perfect
Perfect
2% to 6%
misprediction
(Tournament Branch
Predictor)
64KI, 32KD, 1.92MB
L2, 36 MB L3
??
CPE 432, 10-ILP Limits
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More Realistic HW: Branch Impact
Figure 3.3
Change from Infinite
window to examine to
2048 and maximum
issue of 64 instructions
per clock cycle
60
Instruction issues per cycle
IPC
50
FP: 15 - 45
60
58
48
46
46 45
45
45
41
40
35
Integer: 6 - 12
30
29
19
20
16
15
13
12
14
10
10
9
6
7
6
6
6
7
4
2
2
2
0
gcc
espresso
li
fpppp
doducd
tomcatv
Program
Perfect
Perfect
Tournament
Selective predictor
Standard 2-bit
BHT (512)
Static
Profile
None
No prediction
Limits to ILP HW Model comparison
New Model
Instructions 64
Issued per
clock
Instruction
2048
Window Size
Model
Power 5
Infinite
4
Infinite
200
Renaming
Registers
Infinite v. 256,
Infinite
128, 64, 32, none
48 integer +
40 Fl. Pt.
Branch
Prediction
8K 2-bit
Perfect
Tournament Branch
Predictor
Cache
Perfect
Perfect
Memory
Alias
Perfect
Perfect
64KI, 32KD, 1.92MB
L2, 36 MB L3
Perfect
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More Realistic HW:
Renaming Register Impact (N int + N fp)
Figure 3.5
FP: 11 - 45
70
Change 2048 instr
window, 64 instr
issue, 8K 2 level
Prediction
60
Instruction issues per cycle
IPC
50
59
54
49
45
44
40
35
Integer: 5 - 15
30
29
28
20
20
16
15 15
13
10
11 10 10
12 12 12
11
10
9
5
5
4
15
11
6
4
5
5
5
4
7
5
5
0
gcc
espresso
li
fpppp
doducd
Program
Infinite
Infinite
256
256
128
128
64
32
64
None
32
None
tomcatv
Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions 64
Issued per
clock
Instruction
2048
Window Size
Infinite
4
Infinite
200
Renaming
Registers
256 Int + 256 FP
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Cache
8K 2-bit
Perfect
Tournament
Perfect
Perfect
Memory
Alias
Perfect v. Stack
v. Inspect v.
none
Perfect
64KI, 32KD, 1.92MB
L2, 36 MB L3
Perfect
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More Realistic HW:
Memory Address Alias Impact
Figure 3.6
49
50
40
35
Instruction issues per cycle
45
Change 2048 instr
window, 64 instr
issue, 8K 2 level
Prediction, 256
renaming registers
45
IPC
49
30
25
FP: 4 - 45
(Fortran,
no heap)
Integer: 4 - 9
20
45
16
16
15
15
12
10
10
5
9
7
7
4
5
5
4
3
3
4
6
4
3
5
0
gcc
espresso
li
f pppp
doducd
tomcat v
Program
Perf ect
Perfect
Global/ stack Perf ect
Inspection
Global/Stack perf; Inspec.
heap conflicts
Assem.
None
None
14
4
Limits to ILP HW Model comparison
New Model
Model
Power 5
Instructions
Issued per
clock
Instruction
Window Size
64 (no
restrictions)
Infinite
4
Infinite vs. 256,
128, 64, 32
Infinite
200
Renaming
Registers
64 Int + 64 FP
Infinite
48 integer +
40 Fl. Pt.
Branch
Prediction
Cache
1K 2-bit
Perfect
Tournament
Perfect
Perfect
Memory
Alias
HW
disambiguation
Perfect
64KI, 32KD, 1.92MB
L2, 36 MB L3
Perfect
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Realistic HW: Window Impact
(Figure 3.7)
60
IPC
Instruction issues per cycle
50
40
30
Perfect disambiguation
(HW), 1K Selective
Prediction, 16 entry
return, 64 registers,
issue as many as
window
56
52
47
FP: 8 - 45
45
35
34
22
Integer: 6 - 12
20
15 15
10 10 10
10
9
13
12 12 11 11
10
8
8
6
4
6
3
17 16
14
9
6
4
22
2
15
14
12
9
8
4
9
7
5
4
3
3
6
3
3
0
gcc
expresso
li
f pppp
doducd
tomcat v
Program
Inf inite
256
128
Infinite 256 128
64
32
16
64
32
16
8
8
4
4
16
How to Exceed ILP Limits of this study?
• These are not laws of physics; just practical limits
for today, and perhaps overcome via research
• Compiler and ISA advances could change results
• WAR and WAW hazards through memory:
eliminated WAW and WAR hazards through
register renaming, but not in memory usage
– Can get conflicts via allocation of stack frames as a called
procedure reuses the memory addresses of a previous frame
on the stack
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Limits to ILP
• Doubling issue rates above today’s 3-6
instructions per clock, say to 6 to 12 instructions,
probably requires a processor to
–
–
–
–
issue 3 or 4 data memory accesses per cycle,
resolve 2 or 3 branches per cycle,
rename and access more than 20 registers per cycle, and
fetch 12 to 24 instructions per cycle.
• The complexities of implementing these
capabilities is likely to mean sacrifices in the
maximum clock rate
– E.g, widest issue processor is the Itanium 2, but it also has
the slowest clock rate, despite the fact that it consumes the
most power!
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Limits to ILP
•
•
•
Most techniques for increasing performance increase power
consumption
The key question is whether a technique is energy efficient:
does it increase power consumption faster than it increases
performance?
Multiple issue processors techniques all are energy
inefficient:
1. Issuing multiple instructions incurs some overhead in logic that
grows faster than the issue rate grows
2. Growing gap between peak issue rates and sustained
performance
•
Number of transistors switching = f(peak issue rate), and
performance = f( sustained rate),
growing gap between peak and sustained performance
 increasing energy per unit of performance
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