Transcript Lesson 1 - Introduction - AD Universidad de Oviedo

Electrical Energy
Conversion and
Power Systems
Universidad
de Oviedo
Power Electronic Devices
Semester 1
Power Supply
Systems
Lecturer: Javier Sebastián
Outline

Review of the physical principles of operation of semiconductor
devices.

Thermal management in power semiconductor devices.

Power diodes.

Power MOSFETs.

Power IGBTs

High-power, low-frequency semiconductor devices (thyristors).
2
Electrical Energy
Conversion and
Power Systems
Universidad
de Oviedo
Lesson 4 - Power MOSFET.
Semester 1 - Power Electronic Devices
3
Outline
• The main topics to be addressed in this lesson are the following:
 Review of the basic structure and operation of low-power MOSFETs.
 Internal structures of power MOSFETs.
 Static characteristics of power MOSFETs.
 Dynamic characteristics of power MOSFETs.
 Losses in power MOSFETs.
4
Review of the basic structure of low-power MOSFETs.
Structure
Ohmic contact
Metal
SiO2
S
Name
G
N+
D
Metal
S
G D
Oxide
Semiconductor
N+
P+
Substrate
Schematic
symbol
D (Drain)
Substrate
G (Gate)
D
Schematic
symbol
G
S
P-channel
enhancement MOSFET
S (source) N-channel
enhancement MOSFET
5
Review of the operation of low-power MOSFETs (I).
G
S
D
++ ++
- - - -
+
+
+
+
N+
Depletion layer
(space charge)
N+
V1
P+
Substrate
P-
D
+++
++ ++
+++
-
N+
G
- -
-
N+
A thin layer containing
mobile electrons (minority
carriers) is induced
V2 > V 1
-
S
+
Substrate
6
Review of the operation of low-power MOSFETs (II).
S
N+
G
D
++++ ++++
- - - - - - -
This thin layer containing mobile
electrons (minority carriers) is
called inversion layer
N+
P-
V3 = V TH > V2
+
Substrate
This is a depletion layer
(without carriers)
• When the electron concentration in the new thin layer of electrons is the same
as the hole concentration in the substrate, we say that the inversion process has
started.
• The gate voltage corresponding to this situation is the threshold voltage, VTH.
• It should be noted that the inversion layer is like a new N-type region artificially
created by the gate voltage.
7
Review of the operation of low-power MOSFETs (III).
• Inversion layer when the
voltage between gate and
substrate is higher than VTH.
S
N+
P-
vDS
S
N+
P-
iD
G
+++++ +++++
- - - - - - - - -
Substrate
G
+++++ +++++
- - - - - - - - -
D
N+
V4 > V TH
P
Substrate
D
N+
vGS
• Now, we connect terminal source
to terminal substrate.
• Moreover, we connect a voltage
source between terminals drain and
source.
• How is the drain current iD now?
8
Review of the operation of low-power MOSFETs (IV).
• Now, there is a N-type channel due to the inversion layer.
• This channel allows the current to pass from the drain terminal to the
source terminal.
• With low values of vDS (i.e., vDS << vGS), the channel shape is uniform.
vDS = vDS1 > 0
• If the value of vDS approaches
vGS, then the channel shape is not
uniform any more.
• This is the normal situation
when the MOSFET is working in
linear applications, which is very
different from the case of
switching applications.
S
N+
P-
G
+++++ +++++
- - - - -
- - - - -
Substrate
iD
D
N+
vGS
9
Review of the operation of low-power MOSFETs (V).
• Operation when vGS = 0.
vDS2 > vDS1
vDS1
iD 0
iD 0
S
N+
G
S
D
N+
N+
G
D
N+
P-
PSubstrate
Substrate
• Drain current iD is practically zero when vGS = 0, because no channel exists
between drain and source.
• The same occurs for any vGS < VTH (i.e., iD  0).
10
Review of the operation of low-power MOSFETs (VI)
• Graphical analysis.
iD
2.5kW
D
G
+
-
vGS
S
+
vDS
-
iD [mA]
Load line
4
vGS = 4.5V
vGS = 4V
2
vGS = 3.5V
10V
vGS = 3V
vGS = 2.5V
0
4
VGS = 0V < 2.5V < 3V < 3.5V < 4V < 4.5V
8
12
vDS [V]
vGS < VTH = 2V
Resistive behaviour
Behaviour as current source
Open-circuit behaviour
11
Review of the operation of low-power MOSFETs (VII)
• Parasitic diode.
S
N+
G
D
N+
P-
D
G
S
+
Substrate
• There is a parasitic diode between drain terminal and source
terminal due to the internal connection between substrate
and source.
12
Internal structure of power MOSFETs (I).
• A typical transistor is constituted of several thousand cells.
• As all the FET devices, MOSFET can be easily connected in parallel.
S
• They are vertical MOSFETs.
G
• Examples of cells:
Source
N+
Gate
Source-body
connection
N+
P
N+
NBody
D
Gate
Source
N+
NBody
P
N+
Drain
V-groove MOS (VMOS)
Drain
Double diffused MOSFET (DMOS)
13
Internal structure of power MOSFETs (II).
• Other structures (I):
Gate
Source
N+
Body
Gate
Source-body
connection
Source
P
P
N-
N-
N+
Body
N+
N+
Drain
Drain
MOSFET with trench
gate (UMOSFET)
MOSFET with extending
trench gate (EXTFET)
• The breakdown voltage
is limited to 25 V.
14
Internal structure of power MOSFETs (III).
• Other structures (II):
Gate
Source
N+
Doping
P
N
Body
Source-body
connection
Source-body
connection
P+
ND-source
NA-body
ND-drain-
N+
Body
Drain
P-
N+
N+
NN+
ND-drain+
MOSFET with graded doped
(GD) and trench gate
• Also for low voltage (breakdown
voltage is about 50 V).
Gate
Source
Drain
Structure with charge coupled PN
super-junction in the drift region
(CoolMOS TM)
• 3 times better for 600-800 V devices.
15
Internal structure of power MOSFETs (IV).
• Tridimensional structure of a DMOS:
Gate
Source
P
N+
N+
Drain
Drift region
Body
NN+
16
Packages for power MOSFETs (I).
• Packages are similar to those of power diodes (except axial leaded
through-hole packages).
• There are many different packages.
• Examples: 60V MOSFETs.
RDS(on) = 9.4 mW, ID = 12 A
RDS(on) = 5.5 mW, ID = 86 A
RDS(on) = 9 mW, ID = 93 A
RDS(on) = 12 mW, ID = 57 A
RDS(on) = 1.5 mW, ID = 240 A
17
Packages for power MOSFETs (II).
• Other examples of 60V MOSFETs.
RDS(on) = 3.4 mW, ID = 90 A
18
Information given by the manufacturers.
• Static characteristics:
- Drain-source breakdown voltage.
- Maximum drain current.
- Drain-source on-state resistance.
- Gate threshold voltage.
- Maximum gate to source voltage.
• Dynamic characteristics:
- Parasitic capacitances.
19
Drain-source breakdown voltage, V(BR)DSS.
• It is the drain-source breakdown voltage when the
gate terminal is connected to the source terminal.
ID = 0.25 mA
• It corresponds to a specific value of the drain
current (for example, 0.25 mA).
D
G
S
V(BR)DSS
20
Maximum drain current.
• Manufacturers provide two different values (at least) :
- Maximum continuous drain current, ID.
- Maximum pulse drain current, IDM.
• ID depends on the mounting base (case)
temperature.
• At 100 oC, ID = 23·0.7 = 16.1 A
21
Drain-source on-state resistance, RDS(ON) (I).
• It is one of the most important characteristics in a power MOSFET. The
lower, the better.
• For a given device, its on-resistance decreases with the gate voltage, at least
until this voltage reaches a specific value.
• Power MOSFETs typically increase their on-resistance with temperature.
Under some circumstances, power dissipated in this resistance causes more
heating of the junction, which further increases the junction temperature, in a
positive feedback loop.
• If a MOSFET transistor produces more heat than the heat sink can dissipate,
then thermal runaway can still destroy the transistors. This problem can be
alleviated by lowering the thermal resistance between the transistor die and
the heat sink.
• Thermal runaway refers to a situation where an increase in temperature
changes the conditions in a way that causes a further increase in temperature,
often leading to a destructive result. It is a kind of uncontrolled positive
feedback.
• However, the increase of on-resistance with temperature helps balance
current across multiple MOSFETs (and MOSFET cells) connected in parallel, so
current hogging does not occur.
22
Drain-source on-state resistance, RDS(ON) (II).
• RDS(ON) increases with temperature.
• RDS(ON) decreases with VGS.
Drain-source On Resistance, RDS(on) (Ohms)
23
Drain-source on-state resistance, RDS(ON) (III).
• Comparing different devices with a given value of ID, the value of RDS(on)
increases with V(BR)DSS.
24
Drain-source on-state resistance, RDS(ON) (IV).
• The use of new internal structures (such as charge coupled PN super-junction in the
drift region) has improved the value of RDS(ON) in devices in the range of 600-1000 V.
Year 1984
Year 2000
25
Gate threshold voltage, VGS(TO) (I).
• Manufacturers define VGS(TO) with the gate terminal
connected to the drain terminal and at a specific value
of ID (e.g., 0.25 mA or 1 mA)
• Standard values of VGS(TO) are in the range of 2-4 V.
ID = 1 mA
D
G
S
VGS(TO)
26
Gate threshold voltage, VGS(TO) (II).
• VGS(TO) depends on the temperature:
27
Maximum gate to source voltage, VGS.
• Frequently, this value is ± 20V.
28
Parasitic capacitances in power MOSFETs (I).
• Power MOSFETs are faster than other power devices (such as bipolar
transistors, IGBTs, thyristors, etc.).
• This is because MOSFETs are unipolar devices (no minority carriers are
stored at the edges of PN junctions).
• The switching speed is limited by parasitic capacitances.
• Three parasitic capacitances should be taken into account:
- Cgs, which is a quite linear capacitance.
- Cds, which is a non-linear capacitance.
- Cdg, Miller capacitance, which is also a nonlinear capacitance.
D
Cdg
G
Cgs
S
Cds
29
Parasitic capacitances in power MOSFETs (II).
• Manufacturers provide information about three capacitances, which are
different from the ones mentioned in the previous slide (however, they are
directly related with them):
- Ciss = Cgs + Cgd with Vds=0 (input capacitance). Ciss  Cgs.
- Crss = Cdg (Miller or feedback capacitance).
- Coss = Cds + Cdg (output capacitance). Coss  Cds.
D
D
Cdg
G
Ciss
Cgs
Cdg
S
Cds
G
S
Cds
Coss
Cgs
30
Parasitic capacitances in power MOSFETs (III).
• Example of information provided by manufacturers.
Ciss = Cgs + Cgd
Crss = Cdg
Coss = Cds + Cdg
31
Switching process in power MOSFETs (I).
• Analysis of the switching process assuming:
- Inductive load (frequent situation in power electronics).
- Clamping (or free wheeling) diode.
- Ideal diode.
IL
Cdg
V1
Cds
R
V2
Cgs
32
Switching process in power MOSFETs (II).
• Starting situation:
- The power transistor is off and power diode is on.
 vDG = V2, vDS = V2 and vGS = 0.
- Therefore:
 iDT = 0 and iD = IL.
- From this situation, the mechanical
switch changes from position “B” to “A”.
vDG
-
Cdg
A
V1
B
R
IL
+
iDT
+
-
+
-
-
+
Cds -
+
vGS
iD
Cgs
vDS
V2
33
Switching process in power MOSFETs (III).
vGS
• iDT = 0 while vGS < VGS(TO)
BA
• vDS = V2 while iDT < IL (the diode is on).
VGS(TO)
vDS
This slope depends on R, Cgs and Cdg.
V2
IL
IL iDT
iD
vDG
-
Cdg
A
V1
B
R
+
vGS
-
+
+
-
+
+
-
Cds -
+
-
iDT
Cgs
vDS V2
34
Switching process in power MOSFETs (IV).
vGS
• The current provided by V1 through R is
mainly used to discharge Cdg  almost no
current is used to charge Cgs  vGS = constant.
BA
VGS(TO)
• As a consequence, the Miller plateau appears.
vDS
IL
iDT
IL
vDG
-
Cdg
A
V1
B
R
+
vGS
-
+
iDT
+
-
+
-
Cds -
+
-
+
Cgs
vDS V2
35
Switching process in power MOSFETs (V).
V1
BA
• Cgs y Cdg complete the charging process.
VGS(TO)
The time constant depends on
R, Cgs and Cdg.
vDS
IL
iDT
IL
vDG
-
Cdg
A
V1
B
R
+
vGS
-
+
Cds -
+
-
iDT
+
+
-
vGS
Cgs
vDS V2
36
Switching process in power MOSFETs (VI).
BA
VM
VGS(TO)
vDS
- The control voltage source V1 has to
charge Cgs (large) from 0 to VM and
discharge Cdg (small) from V2 to V2-VM.
- There is high voltage (V2) and increasing
current (from 0 to IL) in the MOSFET at the
same time (from t1 to t2).
iDT
IL
t0 t1 t2 t3
Cdg
PVI
+
vGS
-
+
iDT
• Computing losses between t0 and t2:
+
vGS
V1
-
-
+
+
Cgs Cds -
V2
vDS
37
Switching process in power MOSFETs (VII).
BA
VGS(TO)
V1
VM
- The control voltage source V1 has to
discharge Cdg from V2-VM to -VM.
- There is high current (IL) and
decreasing voltage (from V2 to 0) in the
MOSFET at the same time (from t2 to t3).
vDS
iDT = IL
IL
t0 t1 t2 t3
Cdg
PVI
+
vGS
-
+
iDT
• Computing losses between t2 and t3:
+
vGS
-
-
+
-
+
Cgs Cds -
vDS
IL
38
Switching process in power MOSFETs (VIII).
BA
VGS(TO)
V1
VM
vDS
- The control voltage source V1 has to
charge Cgs from VM to V1 and Cdg from -VM
to -V1.
- There is high current (IL), but the voltage
is very low. Therefore, there are only
conduction losses.
iDT = IL
IL
t0 t1 t2 t3
Cdg
PVI
+
vGS
-
+
iDT
• Computing losses after t3:
+
vGS
-
-
+
-
+
Cgs Cds -
vDS
IL
39
Switching process in power MOSFETs (IX).
• The switching speed strongly depends on the gate
charge Qg. The gate charge is the electric charge that
the driving circuitry must provide for switching the
MOSFET.
vGS
- The driving circuitry must provide the gate-source
charge Qgs from t0 to t2.
iV1
- The driving circuitry must provide the gate-drain
charge Qgd from t2 to t3.
Qgs
t0
- The driving circuitry must provide more electric
charge for the gate voltage to reach the final value
V1. The gate charge Qg includes this charge and the
addition of Qgs + Qgd.
iV1
- For a given driving circuitry, the lower Qg, the faster
the switching process.
V1
- Obviously, t2-t0  QgsR/V1, t3-t2  QdgR/V1 and PV1 =
V1QgfS, where fS is the switching frequency.
Qgd
t2 t3
Qg
R
40
Switching process in power MOSFETs (X).
• Example of information provided by manufacturers:
IRF 540
BUZ80
Year 1984
Year 2000
41
Power losses in power MOSFETs (I).
• Static losses:
- Reverse losses  negligible in practice due to the low value
of the drain current at zero gate voltage, IDSS.
- Conduction losses, due to RDS(on):
PMOS_cond = RDS(ON)·ID_RMS2,
where ID_RMS is the RMS value of the drain current.
• Switching (dynamic) losses:
- Turn-on losses and turn-off losses.
• Driving losses.
42
Power losses in power MOSFETs (II).
vGS
vDS
PMOS_cond = RDS(on)·ID_RMS2
PMOS_S = fS(won + woff)
iDT
PVI
Won
Conduction
losses
Switching losses
Woff
43
Power losses in power MOSFETs (III).
• Driving losses.
vGS
V1
Qgd
iV1
iV1
PV1 = V1QgfS
R
Equivalent circuit
Qgs
t0
iV1
t2 t3
Qg
• It should be noted that for a given MOSFET,
the switching times decrease when R decreases,
thus allowing higher values of iV1.
• Moreover, the lower the switching times, the
lower the switching losses.
V1
RB
Actual circuit to have
low R equivalent values
44
The parasitic diode in power MOSFETs (I).
• It usually is a slow diode, especially in the case of high voltage MOSFETs.
IRF 540
D
G
S
45
The parasitic diode in power MOSFETs (II).
• Case of a high voltage MOSFET structure (e.g., charge coupled PN
super-junction in the drift region).
46