Transcript CS 2204 Fall 2005

CS 2204
Digital Logic
and
State Machine Design
Lab 5
Experiment 1 - 2
Fall 2008

Experiment 2 Lab 5 Outline
 Presentation

Semiconductor technology overview
 Gate Features
 Transistor-Transistor Logic (TTL) overview

Analysis of the term project
 A machine playing strategy
 Analysis of Block 5 of the term project
 Individual work

Experiment 1 is over three weeks : Lab 3, Lab 4 and Lab 5
 Develop a 2-to-1 MUX of Block 4
 Develop a 4-bit 2-to-1 MUX of Block 4

Experiment 2
 Develop a 1-bit Adder (Full Adder) of the Ppm term project
• Use the Algebraic Simplifications Handout to design it
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 2

Xilinx Project Development Steps Today’s work
 Develop the schematic

Design the schematic
 Place the components and wires


Do integrity tests
Test the schematic via logic simulations
What are these
components ?
 Do a Xilinx IMPLEMENTATION

It maps the components to the CLBs of the chip
 Do timing simulations to test the schematic

It generates the bit file
 Download the bit file to the FPGA and test the
design on the board

It programs the chip
CS 2204 Fall 2008
Experiment 1-2 Lab 5
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
Developing a digital product
 A new chip

Which gates & FFs and how many is determined by
 Available components of the technology chosen
 Besides the major operations and speed, cost, power, etc.
product goals of the digital product

FPGAs are used to test the new chip
 A new PCB

Which chips and how many is determined by
 Available chips of the technology chosen
 Besides the major operations and speed, cost, power, etc.
product goals of the digital product
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 4

Gate Features
 Speed, Cost, Power, Size,…

Determined by switch features
 Speed, cost, power, size,…
• Depend on the technology chosen
► CMOS, BiCMOS, TTL, ECL
 They have their own subfamilies
 CMOS : HC, HCT, AC, ACT, FCT,…
 TTL : H, L, S, LS, AS,…
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 5

Gate Speed
 Measured in terms of the gate delay, propagation delay : tp,
nanoseconds today


The time it takes for the gate output to change after an input is
changed
a
Determined by
 The
•
•
 The
•
a
b
technology
ECL is the fastest
CMOS is the slowest
number of inputs
The more inputs, the longer the delay
y
b
y
tp
Today : In terms of nanoseconds or picoseconds
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 6

Gate Speed
 Gate delays are sometimes good

Flip-flops are implemented by taking the advantage of gate
delays
 Without gate delays we could not implement flip-flops
D FF implementation
via gates
D FF
From ON Semiconductor LS TTL Data Manual
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 7

Gate Speed
 Gate delays are often not good

The circuit output is delayed
 We do not have infinite speed

Glitches occur on the outputs
 Outputs change unexpectedly when an input is changed
• If outputs are used during the glitch time, erroneous
results will occur
 A glitch for a circuit happens only if the a specific input
combination is applied first and then another specific input
combination is applied
• For all other input combination pairs, it does not happen
• For the 2-to-1 MUX the specific input combinations are 111
and then 011
CS 2204 Fall 2008
Experiment 1-2 Lab 5
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
Gate delays result in glitches
1
0
1 0
a
a
ab
NOT
AND
b
a
1
c
The output
should not
be zero
momentarily
?
1 1
0
ac
y
OR
AND
1
a
1
1
Do not use the output
during this time
ac
1
0
No !
1 0 1
Glitch
(timing hazard)
CS 2204 Fall 2008
a
ab
y
Experiment 1-2 Lab 5
Page 9

Gate Cost
 How much a gate costs : pennies or less today

Determined by
 The technology
• ECL is the most expensive and TTL is the least
 The number of inputs
• The more inputs, the more expensive
 The number of gates on the chip
• More gates on the chip, the cheaper each gate is

Why are Chips Cheap Today ?
 Silicon is the most common semiconductor
• Sea sand has silicon
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 10

Gate Power Consumption
 Amount of electrical power consumed by a single gate


Micro Watts or less today
Determined by
 The technology
• ECL is the most consuming and CMOS is the least
 The number of inputs
• The more inputs, the higher power consumption
 The speed of the switching elements (transistors)
• The higher the speed, the higher the power consumption
 The higher the power consumption, the higher heat
generated

Indirectly determines the density of the chip
 The number of transistors on the chip
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 11

Gate Size
 How large a gate is
Nanometers on a side today
 Determined by

~3*PL
~5*PL
 Transistor size
• A function of the process length ≡ 65 nanometer
today
• Reason for Moore’s Law
• It will be 0.045 micron soon
 Technology
• The type of the transistor (unipolar vs. bipolar)
• The number of supporting electronic components
(resistors, diodes, capacitors, etc.)
 The number of inputs
• The more inputs, the larger the gate is
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 12

Fan-in
 The number of inputs a gate has
This is purely electrical
 Determined by the technology

 The electronic circuitry determines how many inputs to
have for reliable operation
a
b
c
y
CS 2204 Fall 2008
The fan-in is three
Experiment 1-2 Lab 5
Page 13

Fan-out
 The number of gate inputs that can be connected to
a gate output


This is purely electrical
Determined by the technology
 CMOS gates have the best fan-out

If the fan-out is exceeded
 The output can be physically damaged
 The output value may not be electrically “strong” to be
interpreted as 1 or 0
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Experiment 1-2 Lab 5
Page 14

Fan-out
 In order to increase the fan-out buffers are used

Regular buffers (not input nor output buffers) are used to
increase the fan-out
 A buffer is an electronic circuit that is used to electrically
“drive” large currents, hence many inputs
► It can also have circuits to filter noise and strengthen the
electrical signal
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Experiment 1-2 Lab 5
Page 15
Fan-out


Increasing the fan-out
a
b
y
c
Use a buffer !
But, the input to
output delay is
increased
.....
CS 2204 Fall 2008
.....
Experiment 1-2 Lab 5
Page 16

Digital Engineering Terminology
U1
U2
U2 has no Load
Must be
U2 output is not used corrected
a
Must be
corrected
U4
b
U4 input has no driver
U4 input is not
connected to an output.
Its input value is Hi-Z
(High-Impedance) as
there is infinite
impedance (resistance)
into the U4 input so no
current can flow in
y
a
c
U3
CS 2204 Fall 2008
Must be corrected
Multiple drivers on output y
U3 and U4 outputs are short circuited
Experiment 1-2 Lab 5
Page 17

Technology of components/chips
 Transistor-Transistor Logic (TTL)


Uses bipolar transistors
Consists of two sets of families
 Commercial : 74xxxx
• Cheaper
• Widely available
 Military : 54xxxx
• Manufactured for more stringent applications
• Expensive
Silicon
Silicon Germanium
(SiGe)
Unipolar
CMOS
Gallium
Arsenide
Niobium
(Superconducting)
(Not a semiconductor)
Transistor
type
Bipolar
BiCMOS
SSI MSI LSI VLSI ULSI LSI VLSI ULSI
TTL
Substance
used
Transistor
circuit
ECL
SSI MSI LSI
SSI MSI LSI SSI MSI LSI
faster
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Number of
gates on
the chip
Page 18

Transistor-Transistor Logic (TTL)
 Commercial TTL families, each with a
different combination of speed, power, cost,..
74 (Standard)
 74L (Low-power)
 74S (Schottky)
We will use it
 74LS (Low-power Schottky)
from time to time
 74H (High speed)
 74AS (Advanced Schottky)
 74ALS (Advanced Low-power Schottky)
 74F (Fast)

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Experiment 1-2 Lab 5
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Transistor-Transistor Logic (TTL)

Unused gate input

1) It can be left unconnected (floating)
a
b
y
Implemented by
an available 3input AND gate
a
b
y
From documentation point of it is confusing
If the designer leaves the company and a new engineer
works on it can be confusing
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Experiment 1-2 Lab 5
Page 20

Transistor-Transistor Logic (TTL)

Unused gate input
2) It can be tied to a used input
a
y
b
An available 3-input AND
gate used to implement a
2-input AND gate
 The fan-out of the b signal is increased
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Experiment 1-2 Lab 5
Page 21
Transistor-Transistor Logic (TTL)


Unused gate input
3) It can be connected to 1 or 0 depending on the gate type,
via a pull-up resistor or pull-down resistor
a
a
b
y
b
y
Pull-down
resistor
Pull-up
resistor
+5 v
CS 2204 Fall 2008
0v
Experiment 1-2 Lab 5
Page 22

Transistor-Transistor Logic (TTL)
 Gate outputs

Totem-pole outputs
Do not short circuit
totem-pole gate outputs
2-input NAND gate implementation
From ON Semiconductor LS TTL
Data Manual
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 23

Transistor-Transistor Logic (TTL)
 Gate outputs

Tri-state outputs
 The output has three values !
• 1, 0 and Hi-Z ≡ High-impedance ≡ Floating ≡ Static voltage
• There is an extra control input, Enable, to enable/disable output
► If disabled, the output value is Hi-Z (high-impedance)
a
y
b
Enable
Enable
y
0
Hi-Z
1
ab
Operation table
Tri-state symbol
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Experiment 1-2 Lab 5
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
Transistor-Transistor Logic (TTL)
 Gate outputs

Tri-state outputs
 A tri-state gate can be envisioned as a totem-pole gate with a
switch at the output
y
a
Output y has
three values
a
y
b
b
Enable
Enable
Totem-pole gate
0
CS 2204 Fall 2008
Switch
closed
Switch
open
1
Experiment 1-2 Lab 5
Hi-Z
Page 25

Transistor-Transistor Logic (TTL)
 Gate output

Tri-state outputs
 Outputs can be short circuited if only one gate is enabled at a time
Enable1
You can short circuit
tri-state gate
outputs
Tri-state outputs are often
used to implement buses
A bus line
Enable2
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Experiment 1-2 Lab 5
Page 26

Transistor-Transistor Logic (TTL)
 Gate output

Open-collector
 An external pull-up resistor is needed
a
y
b
Pull-up
resistor
Open collector
symbol
Open-collector outputs are often used
To drive displays and lights
To implement buses
+5 v
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Experiment 1-2 Lab 5
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
Transistor-Transistor Logic (TTL)
 Gate output

Open-collector
 Gate outputs can be short circuited
A bus line
You can short circuit
open-collector gate
outputs
Open-collector outputs are
often short circuited to
implement buses
+5 v
CS 2204 Fall 2008
+5 v
Experiment 1-2 Lab 5
Page 28

Analysis of the Term Project
 The term project black-box view
 The term project operation diagram
 The term project black box partitioning
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 29

The Analysis of the Term Project
 Polytechnic Playing Machine, Ppm

The term project is human vs. machine
 There are two other Ppm versions which are not term
projects


Machine vs. machine
Human vs. human
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 30

The Term Project, Ppm
 The black-box view
From the input devices
13
From page 2 of the Term Project Handout
19
Ppm
To the output devices
Figure 1. The Ppm black box view.

Ppm is sequential (not combinational)
 A large number of FFs are used !
 We need to partition the Ppm based on major operations
• We have to obtain the operation diagram
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 31

Ppm Simplified Operation Diagram
Reset mode
Convert the simplified
operation diagram to
a (detailed) operation
diagram
Press BTN1 4 times
Player 1 mode
Press BTN1
after playing
RD with an
adjacency
Press BTN2 to skip
Press BTN2 after playing
RD without an adjacency
Player 2 mode
Press BTN2
after playing
RD with an
adjacency
Convert each circle
to one or more circles
(steps or states)
Press BTN1 after
playing RD with an
adjacency
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 32
From page 8 of the Term Project Handout
LD6-LD8 on the
FPGA board
show the
current state
Ppm
Input/output
relationship
Ppm
operation
diagram
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 33
Machine play block
Points Calculation block
Human play block
Input/Output Block
Play check block
Machine Play
Block is also
active states
2 and 5
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 34

The Ppm Term Project Partitioning
 Any other major operation ?

Control (time) the operations
 All other operations
CS 2204 Fall 2008
A Digital System
Experiment 1-2 Lab 5
Page 35

The Ppm Term Project
 Ppm is a digital system !
From the input devices
19
13
Ppm
To the output devices
Figure 1. The Ppm black box view.
 The Ppm term project partitioning

First partitioning of the digital system
 Control Unit
 Data Unit

core
Second partitioning (Data Unit partitioning)





Interfacing to the input/output devices core
Handling human player’s play core
Controlling display operations based on game rules core
Calculating new player points core
Determining the machine player play non-core
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 36

The Ppm Digital System Partitioning
From page 9 of the Term Project Handout
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 37

The term project black box partitioning
• Six schematics for six blocks
•
•
•
•
Block 1 : Control Unit : ppm1.sch schematic file
Block 2 : Input/Output : ppm2.sch schematic file
Block 3 : Human Play : ppm3.sch schematic file
Block 4 : Play Check : ppm4.sch schematic file
• Experiment 1 is on a circuit in this block
•
•
Block 5 : Points Calculation : ppm5.sch schematic
file
Block 6 : Machine Play : ppm6.sch schematic file
• The Machine Play Block uses all other blocks except the
Human Play Block
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 38

A Machine Player Strategy
 Its Implementation
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 39

Points Calculation Block, Block 5
 Has 47 inputs and 19 outputs
 Calculates new points for the current player
 Has only combinational circuits
47
Block 5
19
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 40
The Ppm Data Unit
From page 31 of the Term Project Handout

 Block 5, Points Calculation Block
47
CS 2204 Fall 2008
Block 5
Experiment 1-2 Lab 5
19
Page 41

The Ppm Data Unit
 Block 5, Points Calculation Block
47
Block 5
19
 Calculates the new points for the current player

There are several different ways to partition it, one of them
is based on the following major operations :
 Determine the adjacency of the position played
• Adjacency Subblock : NSD
 Determine the regular reward points of the position played
• Reward Calculation Subblock : RWD
 Determine new player points by adding the regular reward
points and the code reward points to the current player points
• Points Subblock : NPT, Ptovf
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 42

Block 5, Points Calculation Block
 The partitioning
47
CS 2204 Fall 2008
1-bit ADDer
circuit
Block 5
Experiment 1-2 Lab 5
19
Page 43

Block 5, Points Calculation Block Development
 Points Calculation Block partitioning
Adjacency
NSD
1-bit ADDer circuit
Adjacency
Subblock
Reward
Calculation
Subblock
Points
Subblock
Regular
Reward
Points
RWD
New Player Points
NPT
CS 2204 Fall 2008
Total Reward Points
TOTRWD
Experiment 1-2 Lab 5
Page 44

Block 5, Points Calculation Block Development
 Adjacency Subblock partitioning
Comparators
MUXes
1-bit ADDer
NSD
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 45

Block 5, Points Calculation Block Development
 Reward Calculation Subblock implementation
MUXes
RWD
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 46

Block 5, Points Calculation Block Development
 Points Subblock partitioning
MUXes
8-bit ADDers
PT
Selplyr
NPT
Ptovf
P2PT
8
P1PT
8
Select Player Points Subsubblock
RWD
TOTRWD
8
CODERWD
8
PT
8
Points Addition Subsubblock
8
8
PT
Ptovf
NPT
Figure 24. The Points Subblock partitioning.
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 47
 The
Ppm Data Unit
 Block 5, Points Calculation Block
There is another major operation left to
implement for Ppm : machine playing
 These two major operations may need to be tightly
coupled if the machine player is highly intelligent

 The course web site term project does not tightly couple
them !
 A real game chip might have to tightly couple them !
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 48
QUESTIONS ?
Make sure you organize your S drive and USB Memory Stick
Make sure you create a CS2204 folder on both
Read slides at the end to learn about the software, Project Manager,
Schematic design and other related topics
Do not leave the lab before your partners finish
► Help your partners
Continue
reading the
Term
Project
handout
Digital
Logic
and
State Machine Design
CS 2204 Fall 2008
Think about
the machine
player
strategy
Experiment 1-2 Lab 5
Page 49

Today’s Individual Xilinx Work
 We will continue to study (analyze) the term project

We will continue with the 4-bit 2-to-1 MUX in Block 3 : Experiment 1
 We will test our (1-bit) 2-to-1 MUX design on the computer assuming real gates
• Do timing simulations
► We will see the glitch due to gate delays

We will use our knowledge of 1-bit ADDers to modify a portion of a term
project to develop a 1-bit ADDer in the Points Calculation Block (Block 5) :
Experiment 2
 The 1-bit ADDer expression is the same as the one obtained in class
• We will replace a 1-bit Xilinx ADDer with our own circuits
 We will perform integrity tests
 We will test our design on the computer
• Do logic simulations
 We will do a Xilinx IMPLEMENTATION of the project
•
To create the bit file
•
•
We will program the FPGA chip ≡ download the bit file
We will use switches and a LED light to test our design on the FPGA board
 We will test our design on the FPGA board
 We will continue reading the Term Project handout

Also read slides at the end to learn about the software, Project Manager,
Schematic design and other related topics
 Help our partners complete today’s project
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 50

1.
Today’s Individual Xilinx Lab Work
Open the ppm project in the exp1 folder
Make sure the Xilinx IMPLEMENTATION is already done
Make sure the team info is placed on the schematic !
2.
Perform functional simulations on the 4-bit MUX in Block 3 of the
term project to refresh your memory
Perform timing simulations on a 2-to-1 MUX to observe the glitch
Copy the exp1 folder and paste it in the cs2204 folder as the exp2
folder
Open the ppm project in the exp2 folder and analyze the project
manager window
Open the schematics and analyze the schematics
3.
4.
5.
6.

7.
8.
9.
10.

We will experiment with the Ppm schematics
Enter team information on the schematics
Study the 4-bit ADDer schematic in the Points Calculation Block in
schematic 5 (ppm5.sch) of the term project to refresh your
memory on the ADDer
Replace the 4-bit ADDer in Block 5 with two gate networks in Block
3 of the term project by using the circuitry shown on page 3 of
Handout 5
Perform integrity tests on the new design
Perform functional simulations on the Full Adder
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 51

Today’s Individual Xilinx Lab Work
11.
12.
Perform a Xilinx IMPLEMENTATION
Test the Xilinx project developed on the FPGA
board
Program the FPGA chip


13.
14.
Test the Ppm to see if it is working
•
Play the game on the FPGA board
Help your partners complete today’s project
Continue Reading the Term Project handout
Study and play the other two types of the Ppm game to
think more about the our machine player’s strategy



Human vs. human : ppmhvsh
Machine vs. machine : ppmhvsh
•

Think about the playing strategy of the machine player that will
be designed
Also read slides at the end to learn about the software,
Project Manager, Schematic design and other related topics
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 52

Today’s Individual Xilinx Lab Work
1.
Open the ppm project in the exp1 folder
a) On the Project Manager window open the Ppm
project in the exp1 folder

Check that the Xilinx IMPLEMENTATION has been
done
• If the IMPLEMENTATION has not been done do it
later as indicated in step 7 below
b) Look at the six Ppm schematics



Remember that if you copy a project, paste it as we did last
week and then open its schematics, the schematics will be all
Non-Project
Therefore, close all these schematics and close the
schematics window
Then, open the schematics one by one on the Project Manager
window, by double clicking on the schematic name on the
upper left side
c) Enter the team information to the schematics if it has not
been entered
d) Save the schematic if the team information is entered
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 53

Today’s Individual Xilinx Lab Work
2. Perform functional simulations on the 4-bit
MUX in Block 3 of the term project to
refresh your memory

Make sure you know how to combine bundles of
related wires to buses to see their simulation
easier
 For example, to combine input wires P1SEL3, P1SEL2,
P1SEL1 and P1SEL0 into bus P1SEL





Select and order them as P1SEL0, P1SEL1, P1SEL2,
P1SEL3 on the simulation window : note the reverse order
Select these four wires
Then, right click on these four wires and select Bus ->
Combine
These four wires will be replaced by P1SEL…(hex)#4
This means there are four P1SEL lines as a bus and their
values will be shown in Hexadecimal
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 54

3.
Today’s Individual Xilinx Work
a)
Perform timing simulations on a 2-to-1 MUX to
observe the glitch
On the functional simulation window, change the type of
the simulation from functional
to glitch
Assign values 1, 1, and 1 to inputs Selplyr, P1SEL0 and
P2SEL0 so that we observe the glitch
Click on the simulation step button several times to
clearly see that the output is 1
Change input a to 0
Again, click on the simulation step button several times
this time to clearly see glitch on the output
Measure the duration of the glitch in terms of
nanoseconds
b)
c)
d)
e)
f)


Do you think you can see this glitch on the FPGA board ?

Why and Why not ?
See the next slide
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 55

Today’s Individual Xilinx Work
3. Perform timing simulations on a 2-to-1 MUX to
observe the glitch
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 56

Today’s Individual Xilinx Lab Work
4.
5.
6.
Copy the exp1 folder and paste it in the cs2204 folder as the
exp2 folder
Open the ppm project in the exp2 folder and analyze the
project manager window
Open the schematics and analyze the schematics




If you copy a project completely as we did and then open its
schematics, the schematics will be all Non-Project
Therefore, close all these schematics and close the schematics
window
Then, open the schematics one by one on the Project Manager
window, by double clicking on the schematic name on the upper
left side
Take a look at the six schematics for the six blocks of the
term project
•
•
•
•
•
•
Block
Block
Block
Block
Block
Block
1 : Control Unit : ppm1.sch schematic file
2 : Input/Output : ppm2.sch schematic file
3 : Human Play : ppm3.sch schematic file
4 : Play Check : ppm4.sch schematic file
5 : Points Calculation : ppm5.sch schematic file
6 : Machine Play : ppm6.sch schematic file
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 57

Today’s Individual Xilinx Lab Work
6. Open the schematics and analyze the
schematics

Enter team information on the schematics
•
•
•
•
•
•
To enter the team info to all the schematics switch to
schematic 1 (ppm1.sch)
Make menu selections File -> Table Setup…
Enter your name and then the name of one of your
partners on Line1:
Enter your other partners’ names on Line 2:
Enter “CS 2204 – Your Lab Section - Fall 2008” on
Line3:
Zoom into the lower right corner of each schematic and
verify that the info is correct
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 58

Today’s Individual Xilinx Lab Work
6.
Open the schematics and analyze the schematics
•
Enter team information on the schematics
•
All project schematics must carry info about the company, designers
and dates of creation and alteration on the lower right side
The CS2204
team
information
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 59

Today’s Individual Xilinx Lab Work
6. Open the schematics and analyze the schematics

Save schematic 1
7. Study the 4-bit ADDer schematic in the Points
Calculation Block in schematic 5 (ppm5.sch) of the
term project to refresh your memory on the ADDer



Switch to schematic 5
Zoom into the upper right area, containing the Encoded
Adjacency Subsubblock
There is a Xilinx macro (a Xilinx Design Block, XDB)

A 4-bit ADDer, ADD4,
•
•
It adds two 4-bit numbers
This Xilinx 4-bit ADDer is used as a 1-bit ADDer
 A Full Adder

See ppm5.sch on the next slide
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 60
Today’s Individual Xilinx Lab Work


Ppm Schematic 5
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Xilinx
4-bit
ADDer
Page 61

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the Points
Calculation Block in schematic 5 (ppm5.sch) of the
term project to refresh your memory on the ADDer

The ADDer is the only component implementing the
Encoded Adjacency Subsubblock
NSD
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 62

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the Points
Calculation Block in schematic 5 (ppm5.sch) of the
term project to refresh your memory on the ADDer


The ADDer is the only component implementing the
Encoded Adjacency Subsubblock
Search for the inputs and outputs of the ADDer by
clicking on the Query window button on top of the
schematic sheet
In the Signal/Bus mode of the SC Query/Find window that
will pop up
Determine which components generate the inputs
 UNENCNSD0, UNENCNSD1, UNENCNSD2
Determine which components use outputs
 NSD0 and NSD1
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 63

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the Points
Calculation Block in schematic 5 (ppm5.sch) of the
term project to refresh your memory on the ADDer

How can I search for a wire in the
schematics ?
 To search for wires press F7 to have the SC
Query/Find window
 Select the Signal/Bus mode
 Click on the input wire, such as UNENCNSD0
 Zoom out completely
 The Xilinx software will show all UNENCNSD0
in red
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 64

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the Points
Calculation Block in schematic 5 (ppm5.sch) of the
term project to refresh your memory on the ADDer
1-bit ADDer circuit : NSD
ADD4
Xilinx
4-bit ADDer
Xilinx does not have
1-bit ADDers
NSD
A Xilinx 4-bit
ADDer is used as
a 1-bit ADDer
Xilinx software
removes logic for
unneeded outputs
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 65

Today’s Individual Xilinx Lab Work
7.
Study the 4-bit ADDer schematic in the Points Calculation
Block in schematic 5 (ppm5.sch) of the term project to
refresh your memory on the ADDer

Xilinx 4-bit ADDer

It is used for Unsigned Binary and 2’s Complement Binary additions
•
•
For Unsigned binary additions, CO indicates the overflow
For 2’s Complement additions, OVL indicates the overflow
Xilinx 4-bit ADDer operation table if A
and B are considered Unsigned Binary
Situation
A + B + CI = K ≤ 15
A + B + CI = K > 15
CS 2204 Fall 2008
Operation
S ≤ 15 ; CO = 0
S = K - 16 ; CO = 1
Experiment 1-2 Lab 5
Page 66
Today’s Individual Xilinx Lab Work

7.
Study the 4-bit ADDer schematic in the Points Calculation
Block in schematic 5 (ppm5.sch) of the term project to
refresh your memory on the ADDer
A 1-bit ADDer (FA)


Converts 3-bit adjacency information (UNENCNSD) to 2-bit
adjacency information NSD
•
Each UNENCNSD bit indicates one adjacency for the played position
 The 1-bit ADDer adds the UNENCNSD bits to count the number of 1s
UNENCNSD2
UNENCNSD2
UNENCNSD2
NSD1
NSD0
Adjacency
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
0
1
1
0
1
1
1
0
2
1
0
0
0
1
1
1
0
1
1
0
2
1
1
0
1
0
2
1
1
1
1
1
3
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 67

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the Points
Calculation Block in schematic 5 (ppm5.sch) of the
term project to refresh your memory on the ADDer

See the correspondence between the Handout 5 circuit
inputs and outputs and Xilinx Adder inputs and outputs

Determine which output is “cout” and which output is the “sum”
output
•
The S0 output is Sum(a, b, c) in Handout 5
 S0 generates NSD0
•
The S1 output is cout(a, b, c) in Handout 5
 S1 generates NSD1
S0 = Sum(a, b, c) = a b c + a b c + a b c + abc = a + b + c
S1 = cout(a, b, c) = bc + ab + ac
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 68

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the Points
Calculation Block in schematic 5 (ppm5.sch) of the
term project to refresh your memory on the ADDer

See the correspondence between the Handout 5 circuit
inputs and outputs and Xilinx Adder inputs and outputs

Determine which input is “a”, which input is “b”, which input is
“c
•
For the Full Adder, inputs a, b and c can be mapped to
UNENCNSD2, UNENCNSD1 and UNENCNSD0 in any order and
so map them as follows
 a = UNENCNSD2
 b = UNENCNSD1
 c = UNENCNSD0
S0 = Sum(a, b, c) = a b c + a b c + a b c + abc = a + b + c
S1 = cout(a, b, c) = bc + ab + ac
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 69

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the
Points Calculation Block in schematic 5
(ppm5.sch) of the term project to refresh
your memory on the ADDer

Observe the internal structure of the Xilinx 4bit ADDer and compare it with the two gate
networks in Handout 5

Do a Hierarchy Push and see that it is implemented by
Xilinx differently from the one discussed in class
• It does not have four cascaded Full Adders !
• See internal implementation of the 4-bit Xilinx
ADDer on the next slide
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 70
Today’s Individual Xilinx Lab Work


Xilinx 4-bit ADDer is not implemented by 1-bit ADDers
Xilinx 4-bit ADDer operation table if A
and B are considered Unsigned Binary
Situation
Operation
A + B + CI = K ≤ 15
S ≤ 15 ; CO = 0
A + B + CI = K > 15
S = K - 16 ; CO = 1
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 71

Today’s Individual Xilinx Lab Work
7. Study the 4-bit ADDer schematic in the
Points Calculation Block in schematic 5
(ppm5.sch) of the term project to refresh
your memory on the ADDer


Close the schematic of the internal circuit of the
Xilinx 4-bit ADDer by means of a Hierarchy Pop
Perform functional simulations on the Full Adder

Use the truth table in Handout 5
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 72

Today’s Individual Xilinx Lab Work
8. Replace the 4-bit ADDer in Block 5 with two
gate networks in Block 3 of the term
project by using the circuitry shown on page
3 of Handout 5

Delete the Xilinx 4-bit ADDer in schematic 5


Do not delete the wires
Save schematic 5, ppm5.sch
•
See modified ppm5.sch on the next slide
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 73
Today’s Individual Xilinx Lab Work


Ppm Schematic 5
CS 2204 Fall 2008
Xilinx
4-bit ADDer
deleted
Experiment 1-2 Lab 5
Page 74

Today’s Individual Xilinx Lab Work
8. Replace the 4-bit ADDer in Block 5 with two gate
networks in Block 3 of the term project by using
the circuitry shown on page 3 of Handout 5


Switch to the Human Play Block, Block 3 or ppm3.sch
Draw the schematic of the 1-bit ADDer by using Handout
5 on the lower left side of the mid area in schematic 5






You will implement the sum and cout outputs by using 2-level
AND-OR gate networks in Handout 5
You will use the Symbols toolbox button on the leftmost side
(or F3) to get the component list
You will use the Draw wires button on the leftmost side (or
F4) to draw wires
To rotate components right press ctrl-r
To rotate components left, press ctrl-l
Note, wires cannot be rotated
• But, by pulling from one end of a wire, it can be rotated !
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 75

Today’s Individual Xilinx Lab Work
8. Replace the 4-bit ADDer in Block 5 with two gate
networks in Block 3 of the term project by using
the circuitry shown on page 3 of Handout 5


Label the wires (inputs and outputs) based on your analysis
in part (7)
Label the components starting at U281


Determine that there is no component labeled U281 and above
How can I search for a component in the schematics, for
example, to search for component U280 ?
•
•
•
•
•



To search for components press F7 to have the SC Query/Find
window
Select the Instance mode
out completely
Enter U280
Zoom The Xilinx software will show the OR gate in a red
rectangle in Block 3
The last component label is U292
Save schematic 3, ppm3.sch
See modified ppm3.sch on next three slides
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 76
Today’s Individual Xilinx Lab Work


The modified ppm3.sch
NSD0
sum
1-bit ADDer
cout
NSD1
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 77
Today’s Individual Xilinx Lab Work


The modified ppm3.sch
NSD0
sum
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 78
Today’s Individual Xilinx Lab Work


The modified ppm3.sch
NSD1
cout
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 79

Today’s Individual Xilinx Lab Work
9. Perform integrity tests on the new design
 The integrity test of the schematic is to see if
there are simple errors to catch


Select Options  Integrity Test

That is why after the Integrity tests we have to perform
• Functional simulations
• Xilinx IMPLEMENTATIONs
• Timing simulations
•
The test window will indicate that the integrity
test passed successfully, but warnings detected
and ask you to read the Project Manager window
for details
Integrity tests do not catch all the errors
10. Perform functional simulations on the Full Adder
Use the truth table in Handout 5
Make sure the circuit is beautified and the schematic is
saved again
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 80

Today’s Individual Xilinx Lab Work
11. Perform a Xilinx IMPLEMENTATION

Make sure there are no errors


Make sure the IMPLEMENTATION options are changed so
that a better IMPLEMENTATION is done
Read the Implementation Log File to confirm that

The number of warnings 19
•
•
These warning are OK, we can continue
Note that there are 19 warnings not 18 as it was the case last
week since a wire in Block 5 is not used
WARNING:NgdBuild:454 - logical net '$Net00170_' has no load
•
•
This wire is the wire that connected the unused data inputs of
the Xilinx 4-bit ADDer to GND in Block 5
Search for this wire by pressing F7 and entering the wire label
'$Net00170_ in the SC Query/Find window
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 81

Today’s Individual Xilinx Lab Work
11. Perform a Xilinx IMPLEMENTATION

Read the Implementation Log File to see that

The FPGA chip utilization is 96%
•
The Xilinx IMPLEMENTATION maps the design to 190
to 191 CLBs, hence 96% to 97% utilization, after an
IMPLEMENTATION, a feature peculiar to FPGA testing
 The conversion of the schematic to the bit file is
“randomized” to have a better mapping of the logic to
CLBs, but it leads to this situation
 That is why we fabricate the prototype chip before we mass
produce it to test the design one more time to make sure
the design is correct
 Nevertheless, the utilization is high since two gate networks
implement a full adder and this implementation is worse than
the Xilinx implementation
 That is why it is better that we use Xilinx components if
they are available
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 82
Today’s Individual Xilinx Lab Work

11.
Perform a Xilinx IMPLEMENTATION

The Project Manager window looks like this after the
IMPLEMENTATION is completed successfully :
Make sure the options
for IMPLEMENTATION
are “High Effort” “50”
and “5”
The checkmark for
IMPLEMENTATION
can be delayed a few
minutes sometimes
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 83

Today’s Individual Xilinx Lab Work
12. Test the Xilinx project developed on the
FPGA board


If it does not work, inspect your circuit in Block
3 and correct your circuit
Do you think there is a possibility of a glitch by
the full adder circuit ?



If yes, which output(s) would have the glitch ?
Which input combination pairs would generate the
glitch ?
Observe the glitch and show it to the TA
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 84

Today’s Individual Xilinx Lab Work
13.
Help your partners complete today’s project
14.
Continue reading the Term Project handout
Study and play the other two types of the Ppm game to
think more about the our machine player’s strategy



Human vs. human : ppmhvsh
Machine vs. machine : ppmhvsh
•

Think about the playing strategy of the machine player that will
be designed
Also read slides at the end to learn about the software,
Project Manager, Schematic design and other related topics
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 85

Understand Critical Wires
RD : 4 bits
 The random digit
P1RD : 4 bits
Next random digit
P2RD : 4 bits
The random digit after next random digit
DISP : 16 bits
 They represent the four position displays
 In Hex
 DISP15-DISP12 : The leftmost position display, PD3
 DISP11-DISP8 : position display PD2, etc
NPDISP : 16 bits
 The result of RD to each display digit
 In Hex
 NPDISP15-NPDISP12 : The leftmost position, PD3, value + RD
 NPDISP11-NPDISP8 : Position display PD2 value + RD
NPSELDISP : 4 bits
 Selects one of NPDISP display values
 In Hex
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 86

Understand Critical Wires
BRWD : 4 bits
 Basic reward
 In Hex
 The digit played and also minimum points earned
 It is selected from RD or NPSELDISP
 Based on how the player played : Directly or with an
addition
Brwdeqz : 1 bit
 BRWD is zero when it is 1
PDPRD : 4 bits
 Display overflow bits after addition
Pdprd : 1 bit
The display overflow bit of the position played
Selplyr : 1 bit
 The current player
 If it is 0, it is the human player, otherwise, it is the machine
player
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 87

Understand Critical Wires
P1SEL : 4 bits
 The position played by the human player
P2SEL : 4 bits
 The position played by the machine player
PSEL : 4 bits
 Position Select bits of current player
ENCPSEL : 2 bits
 The number of the position played
EQ : 4 bits
 The equality of the four displays to the digit played
NSD : 2 bits
 The number of similar digits, i.e. the adjacency information of the
position played
RWD : 8 bits
 The regular reward points calculated based on adjacencies
 In Unsigned Binary
CODERWD : 8 bits
 The code reward points calculated based on the code digits
 In Unsigned Binary
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 88

Understand Critical Wires
P1PT : 8 bits
 Player 1 points
 In Hex
P2PT : 8 bits
 Player 2 points
 In Hex
PT : 8 bits
 The points of the current player
 In Hex
NPT : 8 bits
 New player points for the current player
 In Hex
Ptovf : 1 bit
The points overflow
 if it is 1, the new player points is above (255)10
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 89

Understand Critical Wires
P1add : 1 bit
 Player 1 adds when it is 1
P2add : 1 bit
 Player 2 adds when it is 1
Add : 1 bit
 The current player adds when it is 1
P1skip : 1 bit
 Player 1 skips when it is 1
P2skip : 1 bit
 Player 2 skips when it is 1
P1played : 1 bit
 Player 1 has played when it is 1
P2played : 1 bit
 Player 2 has played when it is 1
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 90

Understand Critical Wires
DISPSEL : 2 bit
 Selects one of four values for displays




00 Selects position displays (displays that RD is played on)
01 Selects player points
10 Selects next two random digits
11 Selects discovered code digits
Add : 1 bit
Shows that the current player has selected to add
Stp1pt : 1 bit
 Store Player 1 points
Stp2pt : 1 bit
 Store Player 2 points
Grd : 1 bit
 Signals to generate a new random digit
 The random digit counter output is stored as P2RD while P2RD and
P1RD are shifted to generate the new P1RD and RD
Bpds : 1 bit
Blink one or all displays slowly
Bpdf : 1 bit
Blocks a display fast after a display overflow
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 91

Understand Critical Wires
Clear : 1 bit
 Clear FFs, registers, counters, etc. during reset in Block 2, Block 4
and Block 6 so that it can play again
Clearp2ffs : 1 bit
 Clears Player 2 FFs, counters and registers
Clff : 1 bit
 Clears FFs in Block 2 so that the next player can play if there is no
overflow
S1 : 1 bit
 State 1 where when it is 1, the Ppm is in state 1
P2sturn : 1 bit
 Signals that Player 2 has the turn
 It is 1 when the Ppm is in state 4
Sysclk : 1 bit
 System clock of the operation diagram at 6 Hz to the digit played
 P2clk : 1 bit
 The clock signal of Player 2 at 48 Hz
 Rdclk : 1 bit

The random digit counter clock at 192 Hz
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 92

Project Manager Actions and Reminders
 Make sure there is a CS2204 folder
 Make sure there is an experiment folder for
the current experiment

You can check the folder the current project is in
by selecting File -> Project Info
 Make sure the FPGA chip and its model are
correct when a new Xilinx project is created

You can check the FPGA chip and its model by
selecting File -> Project Type…
 The selections must be as follows
• The chip : Spartan
• The model : S10PC84
• Speed : 3
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 93

Project Manager Actions and Reminders
 If you copy a project completely and paste it as a
new project, its schematic files cannot be worked on
right away




After you open the schematics, they are all Non-Project
schematics
Close all the schematics
Close the schematics window
Open the schematics one by one on the Project Manager
window
 Double click on the schematic name on the upper left side for
each schematic file
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 94

Project Manager Actions and Reminders
 When you do the first Xilinx
IMPLEMENTATION or after clearing the
implementation data, you need to change
implementation options before clicking on
“Run” in the Implement Design Window

You can change the options by selecting Options…
in the same window and then
 Increase the Place & Route Level to the Highest Effort
on the “Options” window
 Click on the Edit Options… button for Implementation: in
the Program Options area of the “Options” window
 Click on Place and Route on the “Spartan Implementation
Options: Default” window
 Increase Router Options to 50 and 5 for both Routing
Passes and Delay-Based Cleanup Passes
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 95

Project Manager Actions and Reminders
 After a successful IMPLEMENTATION




The schematic files have a check mark next to them
The Design Entry button will have a check mark
The IMPLEMENTATION button has a check mark (after a
delay of minutes sometimes)
The PROGRAMMING button is highlighted
 If not, just click in anywhere in the Flow tab area of the
Project Manager window, it will be highlighted
 If the IMPLEMENTATION is not successful due to
errors, the IMPLEMENTATION button will have an
“X” mark

The error can be because of wrong chip selection or
schematic design errors
 Correct them then !
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 96

Project Manager Actions and Reminders
 After a Xilinx IMPLEMENTATION, read the
Implementation Log File for errors, warnings and
FPGA chip utilization

You can read the Implementation Log File by selecting
Reports -> Implementation Log File
 All No driver warnings must be corrected
• No Driver means, the wire is not connected to any
component output
 All Multiple drivers warnings must be corrected
• Multiple Drivers means, a wire is connected to multiple
component outputs
 Most No Load warnings can be ignored
• Because, the software warns that a component output is
not used, because you do not need the output
• But, if a component output is needed, and not connected,
then it is an error, the output must be connected to the
input of a component
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 97

Project Manager Actions and Reminders
 After performing several Xilinx IMPLEMENTATIONs, clear the
implementation data, by selecting Project -> Clear
Implementation Data

Back to back Xilinx IMPLEMENTATIONs use previous
implementation data that is unchanged to save time
 Over time, this implementation data becomes corrupt and the bit file
has errors
• Correct designs do not perform correctly on the FPGA board

Clearing the implementation data changes the implementation
options to the default ones





The schematic files will keep their check marks
The Design Entry button will keep its check mark
But, the IMPLEMENTATION button will have a question mark
The PROGRAMMING button will not be highlighted
The implementation options must be changed to the required ones again
CS 2204 Fall 2008
Experiment 1-2 Lab 5
Page 98

Schematic Design Actions, Shortcuts &
Reminders
 Place team info on schematics

You can enter the team info by selecting File -> Table
Setup…
 Place your name & a partner name on Line1:
 Place names of the other two partners on Line 2:
 On Line3: place CS2204 – Section A/B/C/D – Fall 2008
 Press F2 to enter the Select & Drag Mode

Only, in this mode components can be deleted, rotated,
copied and pasted
 You can press ESC to enter the Select & Drag Mode
 Press F3 to get component library on screen



VCC is logic 1
GND is logic 0
To quickly locate a component, enter the first few letters of
the component in the bottom area of the SC Symbols window
 To locate XOR gates, just enter letter “X” and “O”
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Experiment 1-2 Lab 5
Page 99

Schematic Design Actions, Shortcuts &
Reminders
 Press F4 to draw wires
 Press F5 to draw buses
 Press F7 to search for wires and components

To search for wires, select the Signal/Bus mode
 If the wire does not have a name, the software assigns one
that starts with a “$” symbol and ends with a “_” symbol
• Use the whole name to search for a wire

To search for a component, select the Instance mode
 If a component does not have a name, the software assigns one
that starts with “$I” symbols followed by a number
• Use the whole name to search for the component
 Press F8 to start simulation quickly
 Press F10 to refresh the screen
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Experiment 1-2 Lab 5 Page 100

Schematic Design Actions, Shortcuts &
Reminders
 Press ctrl-c to copy a wire or a component selected


When components are copied, their labels are not copied !
You can copy from a schematic that belongs to another
project
 To open the schematic of another project, click on
button
in the upper left corner, then select the schematic file which
will be in another folder
 Press ctrl-v to paste a wire or a component
 Press ctrl-r/ctrl-l to rotate components right/left

Wires cannot be rotated !
 You can see how a Xilinx macro is designed (the
internal structure), do a Hierarchy Push, by selecting
Hierarchy -> Hierarchy Push
 You can close the macro internal design screen, by
selecting Hierarchy -> Hierarchy Pop
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Experiment 1-2 Lab 5
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
Schematic Design Actions, Shortcuts & Reminders
 Unless otherwise stated, use Xilinx macros instead of designing
them to save time
 Use buffers to rename wires
 Do not use unnecessary input/output buffers
 Do not use unnecessary input/output pads
 If you copy and paste components, their labels are not copied
and pasted by the software

You will need to “source” the schematic file to copy and paste
component labels as explained in the Advanced Xilinx and Digilent
Features handout
 Xilinx does not have high density ROM memory components

16x1-bit and 32x1-bit
 They may not be used at all
• If needed, its usage is described on page 9 of the Advanced
Xilinx and Digilent Features handout
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Experiment 1-2 Lab 5 Page 102

Schematic Design Actions, Shortcuts & Reminders
 Drawing buses by using Draw Buses button on the left side :


Ppm buses are type None
Individual wires of a bus must have names the same as the bus
name
 The indices of individual wires start at 0 and are up to the number of
bus wires minus 1
• Bus NPT has 8 wires : NPT7, NPT6, NPT5,…, NPT1, NPT0

If a component generates a bus, there is no need to draw the
individual wires of the bus, unless a components needs those
individual wires
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Experiment 1-2 Lab 5 Page 103

Schematic Design Actions, Shortcuts &
Reminders
 Beautify the schematic for documentation purposes

Place components of different sub/blocks separate from
each other to recognize them
 Write Comments, draw lines and rectangles and label
sub/blocks to identify them on the schematic for
documentation purposes
• Use the Graphics Toolbox button on the left :

Label components appropriately
 Wire names follow application and block partitioning naming
requirements
• Except for wires that are connected IBUFs, OBUFs, IPADs and
OPADs
 Component names start with a U
• Except if it is a BUF, IBUF, OBUF, IPAD or OPAD
 To label a component, right click on the component and select
Symbol Properties…
• Give the name in the Reference: section of the Symbol Properties
window
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Experiment 1-2 Lab 5 Page 104

Schematic Design Actions, Shortcuts &
Reminders
 Beautify the schematic for documentation purposes


Do not leave components unused
Draw short wires and label them with the same name
 To label wires double click on the wire and enter the name in
the Net Name: area of the pop up window






Draw wires without unnecessary turn
Draw wires without tangling
Draw wires around components/labels/names
Do not short circuit input lines
Do not short circuit output lines
Do not have labels/attributes/components overlap
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Experiment 1-2 Lab 5 Page 105

Schematic Design Actions, Shortcuts &
Reminders
 Perform integrity tests to catch simple
errors

You can do an integrity test of the current
schematic sheet, by selecting Options -> Integrity
Test for Current Sheet
 After the completion, a window may tell you to look at
the Project Manager window to read about warnings
detected, even if it says the test passed successfully
• Look at the Project Manager window, you will see warnings
in blue
• If the last line has the Schematic Contents OK line, there
is no need to correct anything
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Experiment 1-2 Lab 5 Page 106

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Press F8 to start simulation quickly
 You will see the SC Probes window
 To select the input wires to be simulated, click on the
Stimulator tool button of the SC Probes windows
 Then click on the input wires by precisely clicking on their
names to select them
• There will be a square gray box shown on the left side of the
input wire name
• Wires that have no name cannot be simulated, therefore, they
must be given names for simulation
• When selecting input bus wires, click on the bus wires in the
increasing index order : ABUS0, ABUS1, ABUS2,…
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Experiment 1-2 Lab 5 Page 107

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Press F8 to start simulation quickly
 You will see the SC Probes window :
 To select the output wires to be simulated, click on the Probe
tool button of the SC Probes windows :
 Then click on the output wires by precisely clicking on
their names to select them
• There will be a square gray box shown on the left side of
the output wire name
• Wires that have no name cannot be simulated, therefore,
they must be given names for simulation
• When selecting output bus wires, click on the bus wires in
the increasing index order : OBUS0, OBUS1, OBUS2,…
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Experiment 1-2 Lab 5 Page 108

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Press F8 to start simulation quickly
 You will see the SC Probes window :


To start the simulation, click on the Simulator button of the
SC Probes window :
Once you have the simulation window on the screen
 You will see the input wires listed and then the output wires on
the left side of the Logic Simulator window
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Experiment 1-2 Lab 5 Page 109

Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Separate the input rows from the output rows by placing a
blank row between the input and output wires sets
 Click on the top output wire
 Make selections Signal -> Empty Rows -> Insert

Combine bus bits to reduce the number of rows
 Click on the top bus wire which has the lowest index (ABUS0)
 Press shift and simultaneously click on the highest order bus
wire (ABUS7) to select all the wires of the bus
• A turquoise rectangle covers the bus wires
 Right click on the turquoise rectangle and make the following
selections Bus -> Combine
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Experiment 1-2 Lab 5
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
Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

In order to simulate the circuit, the input wires must be
first given new names
 Click on the Select Stimulators button :
• A keypad window will be shown
 Select an input wire by clicking on it (it will be covered by a
turquoise rectangle) and then click on any letter key on the
keypad, such as “q”
• To the right of the input wire, the new name “q” is shown
• To the right of “q”, the current value of the wire is shown
►
If it is a single wire, the value is Hi-Z
◊ This has to be changed to have correct simulations
► If it is a bus, the value is shown as capital letter “Z”
◊ This has to be changed as well for correct simulations
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Experiment 1-2 Lab 5
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
Schematic Design Actions, Shortcuts & Reminders
 Perform logic simulations to catch logic errors

To change the values of wires on the simulator window
 If it is a single wire, the value is Hi-Z :
• Just click on the Hi-Z line to make the value 0
►The value is shown to the right of name “q” as 0
• Click on the 0 value line again to make the value 1
►The value is shown to the right of name “q” as 1
 If it is a bus, the value is shown as capital letter “Z”
• Click on Logical States to give a value to the bus :
►The Stimulator State Selection window will be shown
• Click on the bus name, such as ABUS
• Enter an appropriate Hex value in the Bus State area, such as “FA”
► Appropriate means the Hex value must fit the width of the
bus : “FA” implies, the bus has at least eight wires
• Click on the Bus button of the Stimulator State Selection window :
►The value assigned is shown to the right of name “q” as “FA”
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Experiment 1-2 Lab 5
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
Schematic Design Actions, Shortcuts & Reminders
 Perform logic simulations to catch logic errors

To change the values of wires on the simulator window
 To have a clock signal as an input follow the steps below :
• Make sure the input signal is not renamed as “q”, “w” etc.
• Click on the input signal to select it
• Click on the Select Stimulators button :
• Click on Formula…
• Double click on C1: under Clocks
• Enter the following in the Edit Formula area :
• 100ns=H 100ns=L
► This means a periodic signal which is 100 ns 1 and 100 ns 0 is generated
► The periodic signal has a period of 200ns or a frequency of 5MHz
• Click Accept
• Click Close
• You will see the C1 button on the Select Stimulators window
highlighted
• Click on C1 so that the input signal is renamed C1
• Click on the Simulation Step button several times :
• You will see the periodic signal automatically generated and the
output values in response to that
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Experiment 1-2 Lab 5
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
Schematic Design Actions, Shortcuts &
Reminders
 Perform logic simulations to catch logic errors

Start simulating the circuit for different input combinations
 If the circuit has 4 or less inputs, then simulate the circuit for
all input combinations (test vectors)
• 16 or less number of input combinations (test vectors)
 If the circuit has more than 4 inputs, select a number of input
combinations (test vectors) then simulate the circuit for these
test vectors
• Which test vectors to choose is a very important task !


To simulate the circuit, click on the Simulation Step button
several times :
Observe the outputs
 If they are correct, try another input combination
 If wrong, return to the schematic and try to figure out why it
is wrong !
 If an output value is Hi-Z or Unknown, there is an error,
correct it
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Experiment 1-2 Lab 5
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
Schematic Design Actions, Shortcuts &
Reminders

Printing schematics
1) Double click on the Printer227 icon on your desktop and
wait about a minute to allow it to affect the printing
option
2) Zoom into an area of the schematic to print the area
3) Select File -> Print on the schematic window
4) Change the option to Current View Only on the Print
window
5) Click on Setup on the Print Window
6) Change the printer to HP Printer 8150 in Room 227
7) Click on Options to select Landscape printing if
necessary
8) Click OK as many times as needed to print the page
9) Print one copy of each area and then make copies of the
printed schematics for your partners
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Experiment 1-2 Lab 5
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

What to do if the testing on the board gives wrong
results even thought the design is correct ?
If the design is absolutely correct, here are the steps to
follow in sequence :
1)
2)
3)
4)
5)
6)
7)
8)
The FPGA board is turned on ?
SW9 is in the PROG position ?
The Bitronics Data Switch selects your PC ?
The FPGA type and model are correct ?
The implementation options are changed ?
There are not too many levels of folders to reach the project on
the PC ?
Clear the implementation data, close the software, restart the
software and do a new Xilinx IMPLEMENTATION

Does it work now ?

Delete the project, recreate the project, copy the schematic design
from the saved schematic file
Save the schematic file worked on in a separate folder

•
Does it work ?
•
Does it work ?
Download the zipped project from the course web site, unzip it, copy
the schematic design from the saved schematic file
CS 2204 Fall 2008
Experiment 1-2 Lab 5
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
What to do if the testing on the board gives
wrong results even thought the design is
correct ?
9) Repeat step 7, by using your partner’s working
schematic
10) Login to another PC and try steps 5 - 8
11) Ask from the TA to help you
a) The TA will login to your original PC and try steps 5 – 8
by using your schematic design and his/her S drive
b) The TA will login to another PC and try steps 5 – 8 by
using your schematic design and his/her S drive on the
new PC
c) The TA will inform the professor
12)If the project works on the second PC, inform
the lab supervisor, Mr. Keni Yip that the original
PC has a problem
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